Abstract: A semiconductor structure includes a first field-effect transistor disposed on a substrate. The first field-effect transistor includes a first metal gate, and a first source/drain region. A second field-effect transistor is vertically stacked above the first field-effect transistor. The second field-effect transistor includes a second metal gate, and a second source/drain region. The first metal gate and the second metal gate are vertically aligned and configured with an air gap disposed therebetween. The first source/drain region and the second source/drain region are vertically aligned and configured with another air gap disposed therebetween.

Abstract: A technique relates to a semiconductor device. A stack is formed over a bottom sacrificial layer, and the bottom sacrificial layer is on a substrate. The bottom sacrificial layer is removed so as to create an opening under the stack, and a dummy gate anchors the stack. A support structure is formed in the opening, and the support structure includes an air gap and is positioned between the stack and the substrate. One or more layers are formed on the support structure. Source or drain regions are formed over the one or more layers, such that the source or drain regions are isolated from the substrate.

Abstract: A method of forming a semiconductor device includes forming a sacrificial epitaxial layer upon a substrate, forming a stack of semiconductor material layers upon the sacrificial epitaxial layer, forming fin mandrels for vertical transistors, selectively etching the sacrificial epitaxial layer beneath the fin mandrels, forming source-drain regions beneath the fin mandrels, selectively removing portions of the fin mandrels creating the fins, and forming source-drain contacts electrically connected to the source-drain regions.

Abstract: A semiconductor device, and method of fabricating the device. The device including a plurality of vertical transistors, each vertical transistor having a raised semiconductor island having a first cross-sectional profile, a source-drain region disposed above the raised semiconductor island, the source-drain region having a second cross-sectional profile, and a semiconductor channel disposed above the source-drain region, the semiconductor channel having a third cross-sectional profile. The second cross-sectional profile is asymmetric.

Abstract: 2D self-aligned contact structures (both gate contact and source/drain contact) are provided that can improve the process control and push further scaling. The 2D self-aligned contact structures can enable tighter process control which can lead to further device scaling. In accordance with the present application, the gate contact structure is confined in one direction by a sacrificial spacer structure that is present in a dielectric material layer, and in another direction by an edge of a metallization structure that is located above the gate contact structure.

Abstract: A CMOS-based resistive processing unit (RPU) and method for a neural network. The RPU includes a capacitor device configured to store a charge representing a weight value associated with a neural network circuit operation. A current source Field Effect Transistor (FET) device is operatively connected to the capacitor device for increasing a charge on the capacitor. A current sink FET device operatively connected to the capacitor device is configured for decreasing the stored capacitor charge. An analog weight update circuit receives one or more update signals generated in conjunction with the neural network circuit operation, the analog weight update circuit controlling the current source FET device and the current sink FET device to provide either a determined amount of current to increase the stored charge on the capacitor device, or sink a determined amount of current to decrease the stored charge on the capacitor device.

Abstract: A substrate structure includes a set of nanosheet layers stacked upon a substrate. The substrate structure includes a p-channel region and an n-channel region. The substrate structure further includes divots within the p-channel region and the n-channel region. A first liner is formed within the divots of the n-channel region. The first liner is formed of a material having a positive charge. A second liner is formed within the divots of the p-channel region. The second liner is formed of a material having a negative charge. A p-type epitaxy is deposited in the p-channel region to form first air gap spacers of the divots in the p-channel region. An n-type epitaxy is deposited in the n-channel region to form second air gap spacers of the divots in the n-channel region.

Abstract: A CMOS-based resistive processing unit (RPU) for a neural network. The RPU includes a capacitor device configured to store a charge representing a weight value associated with a neural network circuit operation. A current source Field Effect Transistor (FET) device is operatively connected to the capacitor device for increasing a charge on the capacitor. A current sink FET device operatively connected to the capacitor device is configured for decreasing the stored capacitor charge. An analog weight update circuit receives one or more update signals generated in conjunction with the neural network circuit operation, the analog weight update circuit controlling the current source FET device and the current sink FET device to provide either a determined amount of current to increase the stored charge on the capacitor device, or sink a determined amount of current to decrease the stored charge on the capacitor device.

Abstract: A semiconductor structure including a bottom source drain region arranged on a substrate, a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region, a metal gate disposed on and around the semiconductor channel region, and a top source drain region above the semiconductor channel region and comprising a first doped epitaxy region and a second doped epitaxy region.

Abstract: A semiconductor device that includes at least one fin structure and a gate structure present on a channel portion of the fin structure. An epitaxial semiconductor material is present on at least one of a source region portion and a drain region portion on the fin structure. The epitaxial semiconductor material includes a first portion having a substantially conformal thickness on a lower portion of the fin structure sidewall and a second portion having a substantially diamond shape that is present on an upper surface of the source portion and drain portion of the fin structure. A spacer present on first portion of the epitaxial semiconductor material.

Abstract: Embodiments are directed to a method and resulting structures for a semiconductor device having reduced parasitic capacitance. A semiconductor fin is formed on a substrate. A first bottom spacer is formed on a surface of the substrate and a sidewall of the semiconductor fin. A sacrificial spacer is formed over a channel region of the semiconductor fin and a portion of the first bottom spacer. A second bottom spacer is formed on a surface of the first bottom spacer and adjacent to the sacrificial spacer. The sacrificial spacer is removed and a conductive gate is formed over the channel region of the semiconductor fin.

Abstract: An integrated circuit having logic and static random-access memory (SRAM) devices includes at least three active regions with gate terminals. Dielectric pillars are disposed between the active regions of the integrated circuit. A pillar is disposed symmetrically between two active regions of the logic device. A pillar is disposed asymmetrically between a p-channel field effect transistor (pFET), and an n-channel field effect transistor (nFET) of the SRAM device.

Abstract: A method is presented for constructing mechanically stable fins. The method includes forming a fin stack including a plurality of sacrificial layers, recessing the fin stack to form channel fins, depositing a first type epitaxy between the channel fins, depositing a dielectric region over the first type epitaxy, depositing a second type epitaxy over the dielectric region, and removing the plurality of sacrificial layers resulting in formation of a plurality of gaps. The method further includes filling a first set of the plurality of gaps with a p-type work function metal (WFM) to form a p-type field effect transistor (pFET) structure and filling a second set of the plurality of gaps with an n-type WFM to form an n-type field effect transistor (nFET) structure, where the nFET structure is stacked over the pFET structure.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of semiconductor layers on a semiconductor substrate, and forming a plurality of gate structures spaced apart from each other on the semiconductor layers. The semiconductor layers are patterned into a plurality of patterned stacks spaced apart from each other, wherein the plurality of patterned stacks are under the plurality of gate structures. The method also includes forming a plurality of sacrificial spacers on lateral sides of the plurality of gate structures, and growing a plurality of source/drain regions. The source/drain regions are adjacent the patterned stacks and include a plurality of pillar portions formed on lateral sides of the sacrificial spacers. The sacrificial spacers and the plurality of pillar portions are removed.

Abstract: Self-limiting cavities are formed within a crystalline semiconductor substrate and beneath a stack of semiconductor layers used to form a nanosheet transistor device. Inner ends of the cavities merge beneath the stack while the outer ends thereof adjoin isolation regions within the substrate. The cavities are filled with electrically insulating material to provide bottom device isolation. Source/drain regions are grown in vertical trenches extending through the stack of semiconductor layers following formation of dielectric inner spacers. The bottom ends of the trenches adjoin the electrically insulating material within the cavities.

Abstract: A neuromorphic device includes a plurality of first control lines, a plurality of second control lines and a matrix of resistive processing unit cells. Each resistive processing unit cell is electrically connected with one of the first control lines and one of the second control lines. A given resistive processing unit cell includes a first resistive device and a second resistive device. The first resistive device is a positively weighted resistive device and the second resistive device is a negatively weighted resistive device.

Abstract: A method for fabricating a semiconductor device includes depositing a sacrificial liner in self-aligned contact openings in first and second regions. The openings are filled with a sacrificial material. The second region is blocked with a first mask to remove the sacrificial material from the first region. The first mask is removed from the second region, and the sacrificial liner is removed from the first region. A first liner is formed in the openings of the first region, and first contacts are formed in the first region on the first liner. The first region is blocked with a second mask to remove the sacrificial material from the second region. The second mask is removed from the first region, and the sacrificial liner is removed from the second region. A second liner is formed in the openings of the second region, and second contacts are formed in the second region.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of semiconductor layers on a semiconductor substrate, and forming a plurality of gate structures spaced apart from each other on the semiconductor layers. The semiconductor layers are patterned into a plurality of patterned stacks spaced apart from each other, wherein the plurality of patterned stacks are under the plurality of gate structures. The method also includes forming a plurality of sacrificial spacers on lateral sides of the plurality of gate structures, and growing a plurality of source/drain regions. The source/drain regions are adjacent the patterned stacks and include a plurality of pillar portions formed on lateral sides of the sacrificial spacers. The sacrificial spacers and the plurality of pillar portions are removed.

Abstract: A vertical injection punchthrough based metal oxide semiconductor (VIPMOS) device and method of manufacturing the same, include a control gate, an erase gate, a floating gate, and an active area where the control gate, the erase gate, and the floating gate are coplanar and perpendicular to the active area.

Abstract: 2D self-aligned contact structures (both gate contact and source/drain contact) are provided that can improve the process control and push further scaling. The 2D self-aligned contact structures can enable tighter process control which can lead to further device scaling. In accordance with the present application, the gate contact structure is confined in one direction by a sacrificial spacer structure that is present in a dielectric material layer, and in another direction by an edge of a metallization structure that is located above the gate contact structure.