Abstract: Provided is a method for forming a semiconductor structure. In embodiments, the method includes forming multiple channel nanosheets in multiple first stacks over a substrate. The channel nanosheets in the first stack define first stack cavities such that each pair of adjacent stacked channel nanosheets in the first stack is separated by one of the first stack cavities. The method further includes forming multiple channel nanosheets in a second stack over a substrate. The channel nanosheets in the second stack defining second stack cavities such that each pair of adjacent stacked channel nanosheets in the first second is separated by one of the second stack cavities. The method further includes filling the first stack cavities with a first gate dielectric material and filling the second stack cavities with a work function metal and a second gate dielectric material. The first gate dielectric material differs from the second gate dielectric material.

Abstract: A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.

Abstract: A method of forming a semiconductor device and resulting device. The method may form a first gate on a gate region of a starting substrate. The starting substrate includes alternating sacrificial layers and semiconductor layers above a buffer sacrificial layer located on a bulk substrate. The method may remove the starting substrate located between the gates. Etching the starting substrate creates a trench into the bulk substrate. The method may form an insulating layer on the inside of the trench. The method may form a masking layer over in the trench in the starting substrate covering a portion of the insulating layer, but below a top surface of the buffer layer. The method may remove the unmasked portion of the insulating layer. The method may form a source/drain in the trench. The method may remove the buffer sacrificial layer, and the sacrificial layers in the layered nanosheet.

Abstract: A method of forming a semiconductor device and resulting device. The method may form a first gate on a gate region of a starting substrate. The starting substrate includes alternating sacrificial layers and semiconductor layers above a buffer sacrificial layer located on a bulk substrate. The method may remove the starting substrate located between the gates. Etching the starting substrate creates a trench into the bulk substrate. The method may form an insulating layer on the inside of the trench. The method may form a masking layer over in the trench in the starting substrate covering a portion of the insulating layer, but below a top surface of the buffer layer. The method may remove the unmasked portion of the insulating layer. The method may form a source/drain in the trench. The method may remove the buffer sacrificial layer, and the sacrificial layers in the layered nanosheet.

Abstract: Structures for spacers of a field-effect transistor and methods for forming such spacers. A mask layer has a feature separated from a vertical sidewall of a first gate structure by a space of predetermined width that exposes a top surface of a semiconductor body. A spacer is formed adjacent to the vertical sidewall of the first gate structure. The spacer has a first section in the space and a second section. The first section of the spacer is located vertically between the second section of the spacer and the top surface of the semiconductor body. The first section of the spacer extends through the space to the top surface of the semiconductor body, and the first section of the spacer fully fills the space.

Abstract: Self-aligned contacts of a semiconductor device are fabricated by forming a metal gate structure on a portion of a semiconductor layer of a substrate. The metal gate structure contacts inner sidewalls of a gate spacer. A second sacrificial epitaxial layer is formed on a first sacrificial epitaxial layer. The first sacrificial epitaxial layer is adjacent to the gate spacer and is formed on source/drain regions of the semiconductor layer. The first and second sacrificial epitaxial layers are recessed. The recessing exposes at least a portion of the source/drain regions. A first dielectric layer is formed on the exposed portions of the source/drain regions, and over the gate spacer and metal gate structure. At least one cavity within the first dielectric layer is formed above at least one of the exposed portions of source/drain regions. At least one metal contact is formed within the at least one cavity.

Abstract: A structure and method of making a semiconductor device includes a single-gated vertical field effect transistor (VFET), that has a first fin on a first bottom source/drain region, a gate of a first work force metal (WFM) surrounding the first fin, and a single gate contact connected to the first WFM. Also included is a double-gated VFET, that has a second fin on a second bottom source/drain region, a first gate of the first WFM disposed on a first side of the second fin, a second wider gate of a second WFM disposed on a second side of the second fin, a first gate contact contacting the first narrow gate, and a second gate contact contacting the second wider gate of the second WFM on the second side.

Abstract: In a fin-Field Effect Transistor (finFET), a recess is created at a location of a fin, the fin being coupled to a gate of the finFET, the recess extending into a substrate interfacing with the gate. The recess is filled at least partially with a first conductive material. The first conductive material is insulated from the gate. The fin is replaced with a replacement structure. The replacement structure is electrically connected to the first conductive material using a second conductive material. the second conductive material is insulated from a first surface of the finFET. A first electrical contact structure is fabricated on the first surface. A second electrical contact structure is fabricated on a second surface of the finFET, the second surface being on a different spatial plane than the first surface.

Abstract: A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins.

Abstract: Techniques for forming closely packed hybrid nanowires are provided. In one aspect, a method for forming hybrid nanowires includes: forming alternating layers of a first and a second material in a stack on a substrate; forming a first trench(es) and a second trench(es) in the stack; laterally etching the layer of the second material selectively within the first trench(es) to form first cavities in the layer; growing a first epitaxial material within the first trench(es) filling the first cavities; laterally etching the layer of the second material selectively within the second trench(es) to form second cavities in the layer; growing a second epitaxial material within the second trench(es) filling the second cavities, wherein the first epitaxial material in the first cavities and the second epitaxial material in the second cavities are the hybrid nanowires. A nanowire FET device and method for formation thereof are also provided.

Abstract: A method of fabricating a top source/drain junction of a vertical transistor includes forming a structure including a bottom source/drain, a fin channel extending vertically from the bottom source/drain, and a gate arranged around the fin channel, the gate including a dielectric layer, a gate metal, and spacers arranged on top and bottom surfaces of the gate; etching to form a recess in a top surface of the fin, the recess having sidewalls that form oblique angles with respect to sidewalls of the fin; forming a top source/drain on the fin and within the recess; doping the top source/drain with a dopant; and annealing to diffuse the dopants from the top source/drain into the fin.

Abstract: A method of fabricating a top source/drain junction of a vertical transistor includes forming a structure including a bottom source/drain, a fin channel extending vertically from the bottom source/drain, and a gate arranged around the fin channel, the gate including a dielectric layer, a gate metal, and spacers arranged on top and bottom surfaces of the gate; etching to form a recess in a top surface of the fin, the recess having sidewalls that form oblique angles with respect to sidewalls of the fin; forming a top source/drain on the fin and within the recess; doping the top source/drain with a dopant; and annealing to diffuse the dopants from the top source/drain into the fin.

Abstract: A device with a vertical transistor and a metal-insulator-metal (MIM) capacitor on a same substrate includes a vertical transistor including a bottom source/drain, a fin channel extending vertically from the bottom source/drain to a top source/drain, and a gate arranged around the fin channel, and the gate including a dielectric layer, a gate metal, and spacers arranged on opposing sides of the gate; and a MIM capacitor including a gate arranged over the bottom source drain, the gate including a gate metal and a dielectric layer, and a metal arranged in a depression in the bottom source/drain and extending through a channel in the gate to cover the gate, the metal directly contacting the dielectric layer of the gate.

Abstract: A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions.

Abstract: A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins.

Abstract: Methods for forming semiconductor devices having non-merged fin extensions. Methods for forming semiconductor devices include forming trenches in an insulator layer of a substrate. Fins are formed in the trenches and a dummy gate is formed over the fins, leaving a source and drain region exposed. The fins are etched below a surface level of a surrounding insulator layer. Fin extensions are epitaxially grown from the etched fins.

Abstract: One illustrative method disclosed herein includes, among other things, forming an initial bottom spacer above a semiconductor substrate and adjacent a vertically-oriented channel semiconductor (VOCS) structure and forming a gate structure around the VOCS structure and above the initial bottom spacer. In this example, the method also includes performing at least one etching process to remove at least a portion of the initial bottom spacer that is positioned vertically under the gate structure so as to thereby result in the formation of an air gap that is positioned under the gate structure, wherein the air gap extends around at least a majority of a perimeter of the VOCS structure, and forming a replacement bottom spacer above the semiconductor substrate and adjacent the air gap.

Abstract: Structures for spacers of a field-effect transistor and methods for forming such spacers. A mask layer has a feature separated from a vertical sidewall of a first gate structure by a space of predetermined width that exposes a top surface of a semiconductor body. A spacer is formed adjacent to the vertical sidewall of the first gate structure. The spacer has a first section in the space and a second section. The first section of the spacer is located vertically between the second section of the spacer and the top surface of the semiconductor body. The first section of the spacer extends through the space to the top surface of the semiconductor body, and the first section of the spacer fully fills the space.

Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.

Abstract: A semiconductor device that includes at least one fin structure and a gate structure present on a channel portion of the fin structure. An epitaxial semiconductor material is present on at least one of a source region portion and a drain region portion on the fin structure. The epitaxial semiconductor material includes a first portion having a substantially conformal thickness on a lower portion of the fin structure sidewall and a second portion having a substantially diamond shape that is present on an upper surface of the source portion and drain portion of the fin structure. A spacer present on first portion of the epitaxial semiconductor material.