Patents by Inventor Chun-Chen Yeh

Chun-Chen Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High thermal budget compatible punch through stop integration using doped glass
    Patent number: 9847388
    Abstract: A method of forming a punch through stop region in a fin structure is disclosed. The method may include forming a doped glass layer on a fin structure and forming a masking layer on the doped glass layer. The method may further include removing a portion of the masking layer from an active portion of the fin structure, and removing an exposed portion the doped glass layer that is present on the active portion of the fin structure. A remaining portion of the doped glass layer is present on the isolation portion of the fin structure. Dopant from the doped glass layer may then be diffused into the isolation portion of the fin structure to form the punch through stop region between the active portion of the fin structure and a supporting substrate.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: December 19, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Sanjay C. Mehta, Xin Miao, Chun-Chen Yeh
  • STRESS MEMORIZATION TECHNIQUE FOR STRAIN COUPLING ENHANCEMENT IN BULK FINFET DEVICE
    Publication number: 20170358496
    Abstract: A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins.
    Type: Application
    Filed: August 25, 2017
    Publication date: December 14, 2017
    Inventors: Kangguo Cheng, Juntao Li, Chun-Chen Yeh
  • FIN FIELD EFFECT TRANSISTOR FABRICATION AND DEVICES HAVING INVERTED T-SHAPED GATE
    Publication number: 20170352744
    Abstract: A method of forming a fin field effect transistor (finFET), including forming a temporary gate structure having a sacrificial gate layer and a dummy gate layer on the sacrificial gate layer, forming a gate spacer layer on each sidewall of the temporary gate structure, forming a source/drain spacer layer on the outward-facing sidewall of each gate spacer layer, removing the dummy gate layer to expose the sacrificial gate layer, removing the sacrificial gate layer to form a plurality of recessed cavities, and forming a gate structure, where the gate structure occupies at least a portion of the plurality of recessed cavities.
    Type: Application
    Filed: June 3, 2016
    Publication date: December 7, 2017
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • FIN FIELD EFFECT TRANSISTOR FABRICATION AND DEVICES HAVING INVERTED T-SHAPED GATE
    Publication number: 20170352659
    Abstract: A method of forming a fin field effect transistor (finFET), including forming a temporary gate structure having a sacrificial gate layer and a dummy gate layer on the sacrificial gate layer, forming a gate spacer layer on each sidewall of the temporary gate structure, forming a source/drain spacer layer on the outward-facing sidewall of each gate spacer layer, removing the dummy gate layer to expose the sacrificial gate layer, removing the sacrificial gate layer to form a plurality of recessed cavities, and forming a gate structure, where the gate structure occupies at least a portion of the plurality of recessed cavities.
    Type: Application
    Filed: April 14, 2017
    Publication date: December 7, 2017
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • PUNCH THROUGH STOPPER IN BULK FINFET DEVICE
    Publication number: 20170323956
    Abstract: A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.
    Type: Application
    Filed: July 21, 2017
    Publication date: November 9, 2017
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Forming vertical transistors and metal-insulator-metal capacitors on the same chip
    Patent number: 9812443
    Abstract: A device with a vertical transistor and a metal-insulator-metal (MIM) capacitor on a same substrate includes a vertical transistor including a bottom source/drain, a fin channel extending vertically from the bottom source/drain to a top source/drain, and a gate arranged around the fin channel, and the gate including a dielectric layer, a gate metal, and spacers arranged on opposing sides of the gate; and a MIM capacitor including a gate arranged over the bottom source drain, the gate including a gate metal and a dielectric layer, and a metal arranged in a depression in the bottom source/drain and extending through a channel in the gate to cover the gate, the metal directly contacting the dielectric layer of the gate.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: November 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • Dual silicide liner flow for enabling low contact resistance
    Patent number: 9805973
    Abstract: A method for fabricating a semiconductor device includes depositing a sacrificial liner in self-aligned contact openings in first and second regions. The openings are filled with a sacrificial material. The second region is blocked with a first mask to remove the sacrificial material from the first region. The first mask is removed from the second region, and the sacrificial liner is removed from the first region. A first liner is formed in the openings of the first region, and first contacts are formed in the first region on the first liner. The first region is blocked with a second mask to remove the sacrificial material from the second region. The second mask is removed from the first region, and the sacrificial liner is removed from the second region. A second liner is formed in the openings of the second region, and second contacts are formed in the second region.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: October 31, 2017
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Controlling channel length for vertical FETs
    Patent number: 9806153
    Abstract: A vertical-type semiconductor device includes a first source/drain (S/D) region on an upper surface of a semiconductor substrate. A channel region is on an upper surface of the first S/D region, and extends along the vertical axis to define a channel length. A second S/D region is on an upper surface of the channel region, and separates the second S/D region from directly contacting the semiconductor substrate. An electrically conductive gate wraps around all outer surfaces of the channel region. The gate extends along the vertical axis to define a gate length that is less than the channel length. Dielectric gate elements are interposed between an upper surface of the gate and a lower surface of the second S/D region, and are configured to electrically insulate the gate from the second S/D region.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: October 31, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • SELF ALIGNED EPITAXIAL BASED PUNCH THROUGH CONTROL
    Publication number: 20170301786
    Abstract: A method of forming a semiconductor device that may include etching source and drain portions of a fin structure of a first semiconductor material selectively to an underlying semiconductor layer of a second semiconductor material, and laterally etching undercut region in the semiconductor layer underlying the fin structure. The method may further include filling the undercut region with a first conductivity type semiconductor material, and forming a second conductivity type semiconductor material for a source region and a drain region on opposing sides of the channel region portion of the fin structure.
    Type: Application
    Filed: December 7, 2016
    Publication date: October 19, 2017
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Buried source-drain contact for integrated circuit transistor devices and method of making same
    Patent number: 9793171
    Abstract: An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filled with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: October 17, 2017
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES INC., STMICROELECTRONICS, INC.
    Inventors: Qing Liu, Ruilong Xie, Chun-Chen Yeh, Xiuyu Cai, William J. Taylor
  • Vertical vacuum channel transistor
    Patent number: 9793395
    Abstract: A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a pattern to elongate the fin and form a second portion of the fin in the substrate, the second portion having a width that is greater than the first portion; oxidizing a region of the second portion of the fin beneath the spacer material to form an oxidized channel region; and removing the oxidized channel region to form a vacuum channel.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: October 17, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC., STMICROELECTRONICS, INC.
    Inventors: Qing Liu, Ruilong Xie, Chun-chen Yeh
  • Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction and semiconductor device having reduced junction leakage
    Patent number: 9793272
    Abstract: A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: October 17, 2017
    Assignees: International Business Machines Corporation, Renesas Electronics Corporation
    Inventors: Dechao Guo, Shogo Mochizuki, Andreas Scholze, Chun-Chen Yeh
  • METHOD OF FORMING EPITAXIAL BUFFER LAYER FOR FINFET SOURCE AND DRAIN JUNCTION LEAKAGE REDUCTION
    Publication number: 20170294510
    Abstract: A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.
    Type: Application
    Filed: June 27, 2017
    Publication date: October 12, 2017
    Inventors: DECHAO GUO, SHOGO MOCHIZUKI, ANDREAS SCHOLZE, CHUN-CHEN YEH
  • Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction
    Patent number: 9786661
    Abstract: A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: October 10, 2017
    Assignees: International Business Machines Corporation, Renesas Electronics Corporation
    Inventors: Dechao Guo, Shogo Mochizuki, Andreas Scholze, Chun-Chen Yeh
  • FABRICATION OF VERTICAL FIELD EFFECT TRANSISTOR STRUCTURE WITH CONTROLLED GATE LENGTH
    Publication number: 20170288039
    Abstract: A method of forming a gate structure, including forming one or more vertical fins on a substrate; forming a bottom spacer on the substrate surface adjacent to the one or more vertical fins; forming a gate structure on at least a portion of the sidewalls of the one or more vertical fins; forming a gauge layer on at least a portion of the bottom spacer, wherein the gauge layer covers at least a portion of the gate structure on the sidewalls of the one or more vertical fins; and removing a portion of the gauge layer on the bottom spacer.
    Type: Application
    Filed: February 22, 2017
    Publication date: October 5, 2017
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • FABRICATION OF VERTICAL FIELD EFFECT TRANSISTOR STRUCTURE WITH CONTROLLED GATE LENGTH
    Publication number: 20170288030
    Abstract: A method of forming a gate structure, including forming one or more vertical fins on a substrate; forming a bottom spacer on the substrate surface adjacent to the one or more vertical fins; forming a gate structure on at least a portion of the sidewalls of the one or more vertical fins; forming a gauge layer on at least a portion of the bottom spacer, wherein the gauge layer covers at least a portion of the gate structure on the sidewalls of the one or more vertical fins; and removing a portion of the gauge layer on the bottom spacer.
    Type: Application
    Filed: November 16, 2016
    Publication date: October 5, 2017
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • EXTENDED CONTACT AREA USING UNDERCUT SILICIDE EXTENSIONS
    Publication number: 20170278942
    Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a contact silicide on a source-drain (S-D) region of a field effect transistor (FET) having extensions by using an undercut etch and a salicide process. A method of forming a contact silicide extension is disclosed. The method may include: forming an undercut region below a dielectric layer and above a source-drain region, the undercut region located directly below a bottom of a contact trench and extending below the dielectric layer to a gate spacer formed on a sidewall of a gate stack; and forming a contact silicide in the undercut region, the contact silicide in direct contact with the source-drain region.
    Type: Application
    Filed: June 9, 2017
    Publication date: September 28, 2017
    Inventors: Effendi Leobandung, Soon-Cheon Seo, Tenko Yamashita, Chun-Chen Yeh
  • Self aligned gate shape preventing void formation
    Patent number: 9773885
    Abstract: A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region. A gate structure present extending from the first fin structure across the isolation region to the second fin structure. The gate structure including a first portion on the first fin structure including a first work function metal having at least one void, an isolation portion that is voidless present overlying the isolation region, and a second portion on the second fin structure including a second work function metal.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: September 26, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC., STMICROELECTRONICS, INC.
    Inventors: Andrew M. Greene, Qing Liu, Ruilong Xie, Chun-Chen Yeh
  • FIN DENSITY CONTROL OF MULTIGATE DEVICES THROUGH SIDEWALL IMAGE TRANSFER PROCESSES
    Publication number: 20170271167
    Abstract: Methods and structures for fabricating fins for multigate devices are disclosed. In accordance with one method, a plurality of sidewalls are formed in or on a plurality of mandrels over a semiconductor substrate such that each of the mandrels includes a first sidewall composed of a first material and a second sidewall composed of a second material that is different from the first material. The first sidewall of a first mandrel of the plurality of mandrels is selectively removed. In addition, a pattern composed of remaining sidewalls of the plurality of sidewalls is transferred onto an underlying layer to form a hard mask in the underlying layer. Further, the fins are formed by employing the hard mask and etching semiconducting material in the substrate.
    Type: Application
    Filed: June 5, 2017
    Publication date: September 21, 2017
    Inventors: Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
  • FinFET having controlled dielectric region height
    Patent number: 9768027
    Abstract: Embodiments are directed to a method of forming a dielectric region of a fin-type field effect transistor (FinFET). The method includes forming at least one fin, and forming a dielectric region adjacent a lower portion of the at least one fin, wherein the dielectric region includes a top surface. The method further includes forming a blocking layer on the top surface of the dielectric region, wherein the blocking layer is configured to prevent at least one subsequent FinFET fabrication operation from impacting the top surface of the dielectric region.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: September 19, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dechao Guo, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh