Patents by Inventor Chun-Chen Yeh

Chun-Chen Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Stress memorization technique for strain coupling enhancement in bulk finFET device
    Patent number: 9761717
    Abstract: A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: September 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Chun-Chen Yeh
  • Trench epitaxial growth for a FinFET device having reduced capacitance
    Patent number: 9755031
    Abstract: A FinFET device includes a semiconductor fin, a gate electrode extending over a channel of the fin and sidewall spacers on each side of the gate electrode. A dielectric material is positioned on each side of a bottom portion of said fin, with an oxide material on each side of the fin overlying the dielectric material. A recessed region, formed in the fin on each side of the channel region, is delimited by the oxide material. A raised source region fills the recessed region and extends from the fin on a first side of the gate electrode to cover the oxide material to a height which is in contact with the sidewall spacer. A raised drain region fills the recessed region and extends from the fin on a second side of the gate electrode to cover the oxide material to a height which is in contact with the sidewall spacer.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: September 5, 2017
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation, GlobalFoundries Inc.
    Inventors: Qing Liu, Xiuyu Cai, Ruilong Xie, Chun-Chen Yeh
  • INCREASED CONTACT AREA FOR FINFETS
    Publication number: 20170250285
    Abstract: This disclosure relates to a fin field effect transistor including a gate structure formed on a fin. Source and drain (S/D) regions are epitaxially grown on the fin adjacent to the gate structure. The S/D regions include a diamond-shaped cross section wherein the diamond-shaped cross section includes: internal sidewalls where the fin was recessed to a reduced height, and an external top portion of the diamond-shaped cross section of the S/D regions. A contact liner is formed over the internal sidewalls and the top portion of the diamond-shaped cross section of the S/D regions; and contacts are formed over the contact liner and over the internal sidewalls and the top portion of the diamond-shaped cross section of the S/D regions.
    Type: Application
    Filed: May 11, 2017
    Publication date: August 31, 2017
    Inventors: Veeraraghavan S. Basker, Chung-Hsun Lin, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Process for integrated circuit fabrication including a uniform depth tungsten recess technique
    Patent number: 9748351
    Abstract: Dummy gates are removed from a pre-metal layer to produce a first opening (with a first length) and a second opening (with a second length longer than the first length). Work function metal for a metal gate electrode is provided in the first and second openings. Tungsten is deposited to fill the first opening and conformally line the second opening, thus leaving a third opening. The thickness of the tungsten layer substantially equals the length of the first opening. The third opening is filled with an insulating material. The tungsten is then recessed in both the first and second openings using a dry etch to substantially a same depth from a top surface of the pre-metal layer to complete the metal gate electrode. Openings left following the recess operation are then filled with a dielectric material forming a cap on the gate stack which includes the metal gate electrode.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: August 29, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC., STMICROELECTRONICS, INC.
    Inventors: Qing Liu, Ruilong Xie, Chun-Chen Yeh
  • Multi-channel gate-all-around FET
    Patent number: 9748352
    Abstract: A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wraparound gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: August 29, 2017
    Assignees: STMicroelectronics, Inc, GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Qing Liu, Ruilong Xie, Chun-chen Yeh, Xiuyu Cai
  • Forming vertical and horizontal field effect transistors on the same substrate
    Patent number: 9741716
    Abstract: A method of forming a vertical FET device and a horizontal FINFET device on a common semiconductor substrate includes forming, on the semiconductor substrate, vertical device fins for the vertical FET device and the horizontal FINFET device with a sacrificial layer and a hard mask (HM) layer. The method also includes forming a vertical FET device doped source and drain (S/D) on the substrate, forming a shallow trench isolation (STI) and a bottom spacer, removing the HM layer and the sacrificial layer for horizontal FINFET device, and forming a sacrificial gate. The method further includes forming an oxide inter dielectric (ILD) layer, and opening the sacrificial gate, forming high-k vertical FET device gate and a high-k horizontal FINFET device gate, and forming contacts.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • TUNNELING FIN TYPE FIELD EFFECT TRANSISTOR WITH EPITAXIAL SOURCE AND DRAIN REGIONS
    Publication number: 20170236755
    Abstract: A method of forming semiconductor devices may begin with forming gate structures over fin structures on sidewalls of at least two mandrels. The mandrels are removed to provide gate structures having a first pitch and gate structure spacers having a second pitch. A first conductivity type epitaxial semiconductor material is formed on the exposed portions of the fin structures. Masking is formed in the first pitch space. The first conductivity type epitaxial semiconductor material is removed from a second space pitch. A second conductivity type epitaxial semiconductor material is formed in the second space pitch.
    Type: Application
    Filed: February 12, 2016
    Publication date: August 17, 2017
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • NANOWIRE SEMICONDUCTOR DEVICE INCLUDING LATERAL-ETCH BARRIER REGION
    Publication number: 20170229553
    Abstract: A semiconductor device includes a semiconductor-on-insulator wafer having a buried layer. The buried layer includes therein opposing etch barrier regions and a gate region between the etch barrier regions. The semiconductor device further includes at least one nanowire having a channel portion interposed between opposing source/drain portions. The channel portion is suspended in the gate region. A gate electrode is formed in the gate region, and completely surrounds all surfaces of the suspended nanowire. The buried layer comprises a first electrical insulating material, and the etch barrier regions comprising a second electrical insulating material different from the first electrical insulating material.
    Type: Application
    Filed: April 24, 2017
    Publication date: August 10, 2017
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Densely spaced fins for semiconductor fin field effect transistors
    Patent number: 9728534
    Abstract: A method of forming a fin-based field-effect transistor device includes forming one or more first fins comprising silicon on a substrate, forming epitaxial layers on sides of the one or more first fins, and removing the one or more first fins to form a plurality of second fins.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: August 8, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
  • Fin density control of multigate devices through sidewall image transfer processes
    Patent number: 9728419
    Abstract: Methods and structures for fabricating fins for multigate devices are disclosed. In accordance with one method, a plurality of sidewalls are formed in or on a plurality of mandrels over a semiconductor substrate such that each of the mandrels includes a first sidewall composed of a first material and a second sidewall composed of a second material that is different from the first material. The first sidewall of a first mandrel of the plurality of mandrels is selectively removed. In addition, a pattern composed of remaining sidewalls of the plurality of sidewalls is transferred onto an underlying layer to form a hard mask in the underlying layer. Further, the fins are formed by employing the hard mask and etching semiconducting material in the substrate.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: August 8, 2017
    Assignee: International Business Machines Corporation
    Inventors: Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
  • NANOWIRE SEMICONDUCTOR DEVICE INCLUDING LATERAL-ETCH BARRIER REGION
    Publication number: 20170221991
    Abstract: A semiconductor device includes a semiconductor-on-insulator water having a buried layer. The buried layer includes therein opposing etch barrier regions and a gate region between the etch barrier regions. The semiconductor device further includes at least one nanowire having a channel portion interposed between opposing source/drain portions. The channel portion is suspended in the gate region. A gate electrode is formed in the gate region, and completely surrounds all surfaces of the suspended nanowire. The buried layer comprises a first electrical insulating material, and the etch barrier regions comprising a second electrical insulating material different from the first electrical insulating material.
    Type: Application
    Filed: April 14, 2017
    Publication date: August 3, 2017
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Low Resistance Source Drain Contact Formation with Trench Metastable Alloys and Laser Annealing
    Publication number: 20170213739
    Abstract: Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5×1021 atoms per cubic centimeter (at./cm3). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.
    Type: Application
    Filed: January 22, 2016
    Publication date: July 27, 2017
    Inventors: Oleg Gluschenkov, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi, Tenko Yamashita, Chun-chen Yeh
  • Low Resistance Source Drain Contact Formation
    Publication number: 20170213889
    Abstract: Techniques for forming Ga-doped source drain contacts in Ge-based transistors are provided. In one aspect, a method for forming Ga-doped source and drain contacts includes the steps of: depositing a dielectric over a transistor; depositing a dielectric over the transistor; forming contact trenches in the dielectric over, and extending down to, source and drain regions of the transistor; depositing an epitaxial material into the contact trenches; implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer; and annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration of greater than about 5×1020 at./cm3. Transistor devices are also provided utilizing the present Ga-doped source and drain contacts.
    Type: Application
    Filed: January 22, 2016
    Publication date: July 27, 2017
    Inventors: Oleg Gluschenkov, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi, Chun-chen Yeh
  • Extended contact area using undercut silicide extensions
    Patent number: 9716160
    Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a contact silicide on a source-drain (S-D) region of a field effect transistor (FET) having extensions by using an undercut etch and a salicide process. A method of forming a contact silicide extension is disclosed. The method may include: forming an undercut region below a dielectric layer and above a source-drain region, the undercut region located directly below a bottom of a contact trench and extending below the dielectric layer to a gate spacer formed on a sidewall of a gate stack; and forming a contact silicide in the undercut region, the contact silicide in direct contact with the source-drain region.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: July 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Soon-Cheon Seo, Tenko Yamashita, Chun-Chen Yeh
  • Reduced capacitance in vertical transistors by preventing excessive overlap between the gate and the source/drain
    Patent number: 9716170
    Abstract: Embodiments of the invention are directed to a vertical FET device having gate and source or drain features. The device includes a fin formed in a substrate and a source or a drain region formed in the substrate. The device further includes a trench formed in the source or the drain region and a dielectric region formed in the trench. The device further includes a gate formed along vertical sidewalls of the fin and positioned such that a space between the gate and the source or the drain region includes at least a portion of the dielectric region. In some embodiments, the device further includes a bottom spacer formed over an upper surface of the dielectric region and positioned such that the space between the gate and the source or the drain region further includes at least a portion of the bottom spacer.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: July 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-chen Yeh
  • Method and structure for multigate FinFET device epi-extension junction control by hydrogen treatment
    Patent number: 9711645
    Abstract: Embodiments are directed to forming a structure comprising at least one fin, a gate, and a spacer, applying an annealing process to the structure to create a gap between the at least one fin and the spacer, and growing an epitaxial semiconductor layer in the gap between the spacer and the at least one fin.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: July 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-chen Yeh
  • Fabrication of vertical field effect transistor structure with controlled gate length
    Patent number: 9711618
    Abstract: A method of forming a gate structure, including forming one or more vertical fins on a substrate; forming a bottom spacer on the substrate surface adjacent to the one or more vertical fins; forming a gate structure on at least a portion of the sidewalls of the one or more vertical fins; forming a gauge layer on at least a portion of the bottom spacer, wherein the gauge layer covers at least a portion of the gate structure on the sidewalls of the one or more vertical fins; and removing a portion of the gauge layer on the bottom spacer.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: July 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • SELF ALIGNED GATE SHAPE PREVENTING VOID FORMATION
    Publication number: 20170200807
    Abstract: A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region. A gate structure present extending from the first fin structure across the isolation region to the second fin structure. The gate structure including a first portion on the first fin structure including a first work function metal having at least one void, an isolation portion that is voidless present overlying the isolation region, and a second portion on the second fin structure including a second work function metal.
    Type: Application
    Filed: March 28, 2017
    Publication date: July 13, 2017
    Inventors: Andrew M. Greene, Qing Liu, Ruilong Xie, Chun-Chen Yeh
  • METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH FILLED GATE LINE END RECESSES
    Publication number: 20170200812
    Abstract: A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions.
    Type: Application
    Filed: March 29, 2017
    Publication date: July 13, 2017
    Inventors: XIUYU CAI, QING LIU, KEJIA WANG, RUILONG XIE, CHUN-CHEN YEH
  • STRESS MEMORIZATION TECHNIQUE FOR STRAIN COUPLING ENHANCEMENT IN BULK FINFET DEVICE
    Publication number: 20170194206
    Abstract: A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins.
    Type: Application
    Filed: March 23, 2017
    Publication date: July 6, 2017
    Inventors: Kangguo Cheng, Juntao Li, Chun-Chen Yeh