Patents by Inventor Chun Chieh

Chun Chieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220035405
    Abstract: A pressing device includes a base board unit including at least two coupling members, an upper board unit including a trigger switch and at least two engaging members, and two interlocking members disposed between the upper board unit and the base board unit. Each interlocking member has at least one coupling portion coupled with a respective coupling member, at least one engaging portion coupled with a respective engaging member, and at least one locking set. The locking set of one interlocking member is coupled with the locking set of the other interlocking member. When the upper board unit is pressed, the interlocking members are pivoted and the trigger switch is converted from an initial state to a triggered state.
    Type: Application
    Filed: November 10, 2020
    Publication date: February 3, 2022
    Applicant: SUNREX TECHNOLOGY CORP.
    Inventors: Shih-Pin LIN, Chun-Chieh CHEN, Ling-Cheng TSENG, Yu-Shuo YANG
  • Publication number: 20220037203
    Abstract: An opening is formed through a dielectric material layer to physically expose a top surface of a conductive material portion in, or over, a substrate. A metallic nitride liner is formed on a sidewall of the opening and on the top surface of the conductive material portion. A metallic adhesion layer including an alloy of copper and at least one transition metal that is not copper is formed on an inner sidewall of the metallic nitride liner. A copper fill material portion may be formed on an inner sidewall of the metallic adhesion layer. The metallic adhesion layer is thermally stable, and remains free of holes during subsequent thermal processes, which may include reflow of the copper fill material portion. An additional copper fill material portion may be optionally deposited after a reflow process.
    Type: Application
    Filed: July 29, 2020
    Publication date: February 3, 2022
    Inventors: Cheng-Lun TSAI, Huei-Wen HSIEH, Chun-Sheng CHEN, Kai-Shiang KUO, Jen-Wei LIU, Cheng-Hui WENG, Chun-Chieh LIN, Hung-Wen SU
  • Patent number: 11239354
    Abstract: A transistor device having fin structures, source and drain terminals, channel layers and a gate structure is provided. The fin structures are disposed on a material layer. The fin structures are arranged in parallel and extending in a first direction. The source and drain terminals are disposed on the fin structures and the material layer and cover opposite ends of the fin structures. The channel layers are disposed respectively on the fin structures, and each channel layer extends between the source and drain terminals on the same fin structure. The gate structure is disposed on the channel layers and across the fin structures. The gate structure extends in a second direction perpendicular to the first direction. The materials of the channel layers include a transition metal and a chalcogenide, the source and drain terminals include a metallic material, and the channel layers are covalently bonded with the source and drain terminals.
    Type: Grant
    Filed: July 12, 2020
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lu, Chao-Ching Cheng, Tzu-Ang Chao, Lain-Jong Li
  • Patent number: 11239092
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The first layer is made of a semiconductor material. The method includes forming a stop layer over the first layer. The method includes forming a second layer over the stop layer. The second layer is in direct contact with the stop layer. The method includes removing the second layer. The method includes performing an etching process to remove the stop layer and an upper portion of the first layer. The method includes performing a first planarization process over the first layer.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Yu-Chen Wei, Chun-Chieh Chan, Chun-Jui Chu, Jen-Chieh Lai, Shih-Ho Lin
  • Publication number: 20220030128
    Abstract: An office machine with intelligent sleep and wake function and a control method thereof are introduced. The office machine comprises a storage module, image module, processing module, and power supply module. The processing module is connected to the storage module, image module, and power supply module. The storage module stores user data and first feature data. The processing module obtains a user image from the image module to generate second feature data and then process the first and second feature data to generate comparison result information. After determining user confirmation information according to the comparison result information, the processing module sends a first control signal to the power module, such that the office machine wakes up automatically from sleep. The office machine wakes up automatically when a user approaches the office machine, so as to save time and improve work efficiency and ease of use.
    Type: Application
    Filed: June 23, 2021
    Publication date: January 27, 2022
    Inventor: CHUN-CHIEH LIAO
  • Publication number: 20220029008
    Abstract: A device includes a first transistor and a second transistor. The first transistor includes a first gate terminal coupled to the first source terminal, a first source terminal, and a first drain terminal. The second transistor includes a second gate terminal coupled to the first drain terminal, a second source terminal, and a second drain terminal.
    Type: Application
    Filed: July 23, 2020
    Publication date: January 27, 2022
    Inventors: Chun-Chieh YANG, Yue-Ming HSIN, Yi-Nan ZHONG, Yu-Chen LAI
  • Patent number: 11233123
    Abstract: The present disclosure describes an exemplary method to form p-type fully strained channel (PFSC) or an n-type fully strained channel (NFSC) that can mitigate epitaxial growth defects or structural deformations in the channel region due to processing. The exemplary method can include (i) two or more surface pre-clean treatment cycles with nitrogen trifluoride (NF3) and ammonia (NH3) plasma, followed by a thermal treatment; (ii) a prebake (anneal); and (iii) a silicon germanium epitaxial growth with a silicon seed layer, a silicon germanium seed layer, or a combination thereof.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: January 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shahaji B. More, Huai-Tei Yang, Zheng-Yang Pan, Shih-Chieh Chang, Chun-Chieh Wang, Cheng-Han Lee
  • Patent number: 11232945
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: January 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei Chang, Min-Hsiu Hung, Hung-Yi Huang, Chun Chieh Wang, Yu-Ting Lin
  • Publication number: 20220021396
    Abstract: A signal converting apparatus includes a comparing device, a first digital-slope quantizer, and a second digital-slope quantizer. The comparing device having a first input terminal and a second input terminal for receiving a first received signal and a second received signal, and for generating an output signal at an output port. The first digital-slope quantizer generates a first set of digital signals to monotonically adjust the first received signal and the second received signal at the first input terminal and the second input terminal during a first phase according to a first quantization unit. The second digital-slope quantizer generates a second set of digital signals to monotonically adjust the first received signal and the second received signal at the first input terminal and the second input terminal during a second phase after the first phase according to a second quantization unit.
    Type: Application
    Filed: September 30, 2021
    Publication date: January 20, 2022
    Applicant: TRON FUTURE TECH INC.
    Inventors: Yu-Jiu WANG, Chun-Chieh PENG, Ta-Shun CHU
  • Patent number: 11227828
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a capacitor structure, and a conductive contact. The semiconductor substrate has at least one semiconductor fin thereon. The gate structure is disposed across the semiconductor fin. The capacitor structure is disposed on the gate structure. The capacitor structure includes a ferroelectric layer and a first metal layer disposed on the ferroelectric layer. The capacitor structure is sandwiched between the conductive contact and the gate structure.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Ho, Chun-Chieh Lu, Chih-Sheng Chang
  • Patent number: 11227955
    Abstract: A semiconductor device includes a substrate, a first poly-material pattern, a first conductive element, a first semiconductor layer, and a first gate structure. The first poly-material pattern is over and protrudes outward from the substrate, wherein the first poly-material pattern includes a first active portion and a first poly-material portion joined to the first active portion. The first conductive element is over the substrate, wherein the first conductive element includes the first poly-material portion and a first metallic conductive portion covering at least one of a top surface and a sidewall of the first poly-material portion. The first semiconductor layer is over the substrate and covers the first active portion of the first poly-material pattern and the first conductive element. The first gate structure is over the first semiconductor layer located within the first active portion.
    Type: Grant
    Filed: September 22, 2019
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Ching Cheng, Chun-Chieh Lu, Hung-Li Chiang, Tzu-Chiang Chen
  • Publication number: 20220013353
    Abstract: A method includes: providing a bottom layer; depositing a first seed layer over the bottom layer, the first seed layer having at least one of a tetragonal crystal phase and an orthorhombic crystal phase; depositing a dielectric layer over the bottom layer adjacent to the first seed layer, the dielectric layer including an amorphous crystal phase; depositing an upper layer over the dielectric layer; performing a thermal operation on the dielectric layer; and cooling the dielectric layer, wherein after the cooling the dielectric layer becomes a ferroelectric layer.
    Type: Application
    Filed: July 9, 2020
    Publication date: January 13, 2022
    Inventors: CHUN-CHIEH LU, SAI-HOOI YEONG, YU-MING LIN
  • Publication number: 20220014649
    Abstract: A scaler includes an input interface, an output Vsync pulse generating circuit and a data buffer circuit. The input interface is arranged to receive an input Vsync pulse and input image data. The output Vsync pulse generating circuit is arranged to accordingly generate a first output Vsync pulse and a first output request in response to the input Vsync pulse. The data buffer circuit is arranged to buffer the input image data and, in response to the first output request, output a first output frame according to the input image data. The output Vsync pulse generating circuit further generates a second output Vsync pulse and a second output request according to the first output Vsync pulse and a first predetermined period and in response to the second output request, the data buffer circuit further outputs a second output frame according to the input image data.
    Type: Application
    Filed: May 27, 2021
    Publication date: January 13, 2022
    Inventors: Ying-Hsin Lin, Wen-Hsia Kung, Chun-Chieh Chan
  • Patent number: 11222784
    Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: January 11, 2022
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
  • Patent number: 11223749
    Abstract: A scaler includes an input interface, an output Vsync pulse generating circuit and a data buffer circuit. The input interface is arranged to receive an input Vsync pulse and input image data. The output Vsync pulse generating circuit is arranged to accordingly generate a first output Vsync pulse and a first output request in response to the input Vsync pulse. The data buffer circuit is arranged to buffer the input image data and, in response to the first output request, output a first output frame according to the input image data. The output Vsync pulse generating circuit further generates a second output Vsync pulse and a second output request according to the first output Vsync pulse and a first predetermined period and in response to the second output request, the data buffer circuit further outputs a second output frame according to the input image data.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: January 11, 2022
    Assignee: Realtek Semiconductor Corp.
    Inventors: Ying-Hsin Lin, Wen-Hsia Kung, Chun-Chieh Chan
  • Patent number: 11214858
    Abstract: A mask plate and a mask sheet are provided. The mask plate includes a first mask sheet and a second mask sheet, the first mask sheet includes a first mask area located in a middle region of the first mask sheet and first peripheral areas located on both sides of the first mask area in a first direction, a thickness of the first mask area is less than a thickness of the first peripheral areas to form a first concave portion; the second mask sheet includes a second mask area located in a middle region of the second mask sheet and second peripheral areas located on both sides of the second mask area in a second direction, a thickness of the second mask area is less than a thickness of the second peripheral areas to form a second concave portion.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: January 4, 2022
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Long Jin, Fuqiang Tang, Chun Chieh Huang, Yu Jing
  • Publication number: 20210409642
    Abstract: The present invention discloses a signal enhancement relay apparatus is provided. A display data channel stretching circuit includes a direct and an indirect channels. A snooper circuit is disposed at the direct channel. The indirect channel includes a master and a slave paths having a master and a slave transmission circuits disposed thereon. The direct channel is selected under a default passive mode such that a snooper link bridging handler circuit is enabled to monitor a display data transmission on the direct path through the snooper circuit, to perform a channel link bridging process corresponding to a data enhancement transmission channel accordingly.
    Type: Application
    Filed: May 7, 2021
    Publication date: December 30, 2021
    Inventors: CHUN-CHIEH CHAN, CHIA-HAO CHANG, TAI-JUNG WU, MING-AN WU
  • Publication number: 20210399635
    Abstract: A control circuit of a power converter is coupled to an output stage and controls it to convert an input voltage into an output voltage and generate an output current. The control circuit includes a ripple generation circuit, a synthesis circuit, an error amplifier, a comparator and a PWM circuit. The ripple generation circuit generates a ripple signal according to an input voltage, an output voltage and output current. The synthesis circuit receives the ripple signal and a first feedback signal related to output voltage to provide a second feedback signal. The error amplifier receives the second feedback signal and a reference voltage to generate an error signal. The comparator receives a ramp signal and error signal to generate a comparison signal. The PWM circuit generates a PWM signal to control output stage according to the comparison signal. A slope of ripple signal is changed with the output current.
    Type: Application
    Filed: June 8, 2021
    Publication date: December 23, 2021
    Inventors: Chih-Lien CHANG, Chun-Chieh WANG
  • Publication number: 20210399136
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate layer, a low-doping semiconductor layer, a crystalline ferroelectric layer and source and drain terminals. The crystalline ferroelectric layer is disposed between the gate layer and the low-doping semiconductor layer. The source terminal and the drain terminal are disposed on the low-doping semiconductor layer.
    Type: Application
    Filed: December 16, 2020
    Publication date: December 23, 2021
    Inventors: Georgios Vellianitis, Chun-Chieh Lu, Sai-Hooi Yeong, Mauricio Manfrini
  • Publication number: 20210398991
    Abstract: A ferroelectric tunnel junction (FTJ) memory device includes a bottom electrode located over a substrate, a top electrode overlying the bottom electrode, and a ferroelectric tunnel junction memory element located between the bottom electrode and the top electrode. The ferroelectric tunnel junction memory element includes at least one ferroelectric material layer and at least one tunneling dielectric layer.
    Type: Application
    Filed: April 14, 2021
    Publication date: December 23, 2021
    Inventors: Mauricio MANFRINI, Sai-Hooi YEONG, Han-Jong CHIA, Bo-Feng YOUNG, Chun-Chieh LU