Abstract: A rotary coding disc and a method for designing the same is applied to an optical encoder. N-bit De Bruijn sequences include 1 and 0. The N-bit De Bruijn sequence has the maximum binary code and the minimum binary code. When a binary code having M bits is located between the maximum binary code and the minimum binary code, the corresponding N-bit De Bruijn sequences are selected as diagonal De Bruijn sequences, wherein 2 N - 2 ? N 2 - N 2 < M < 2 N - 2 ? N 2 + N 2 . The De Bruijn sequence may be converted into a De Bruijn energy level. The total number of 1 consecutively neighboring 0 and (N?1) consecutively neighboring N of the De Bruijn energy level is calculated. The transparent areas and the opaque areas are located based on the De Bruijn sequence or the De Bruijn energy level that corresponds to the total number less than or equal to N.

Abstract: A method includes forming an insulating layer over a conductive feature; etching the insulating layer to expose a first surface of the conductive feature; covering the first surface of the conductive feature with a sacrificial material, wherein the sidewalls of the insulating layer are free of the sacrificial material; covering the sidewalls of the insulating layer with a barrier material, wherein the first surface of the conductive feature is free of the barrier material, wherein the barrier material includes tantalum nitride (TaN) doped with a transition metal; removing the sacrificial material; and covering the barrier material and the first surface of the conductive feature with a conductive material.

Abstract: A method for CMP includes following operations. A dielectric structure is received. The dielectric structure includes a metal layer stack formed therein. The metal layer stack includes at least a first metal layer and a second metal layer, and the first metal layer and the second metal layer are exposed through a surface of the dielectric structure. A first composition is provided to remove a portion of the first metal layer from the surface of the dielectric structure. A second composition is provided to form a protecting layer over the second metal layer. The protecting layer is removed from the second metal layer. A CMP operation is performed to remove a portion of the second metal layer. In some embodiments, the protecting layer protects the second metal layer during the removal of the portion of the first metal layer.

Abstract: A method for CMP includes following operations. A metal layer is received. A CMP slurry composition is provided in a CMP apparatus. The CMP slurry composition includes at least a first oxidizer and a second oxidizer different from each other. The first oxidizer is oxidized to form a peroxidant by the second oxidizer. A portion of the metal layer is oxidized to form a first metal oxide by the peroxidant. The first metal oxide is re-oxidized to form a second metal oxide by the second oxidizer.

Abstract: The invention introduces a non-transitory computer program product for scheduling execution of host commands when executed by a processing unit of a flash controller. Space of a random access memory of the flash controller is allocated for a first queue and a second queue, and the first queue stores the host commands issued by a host side in an order of time when the host commands arrive to the flash controller. The non-transitory computer program product includes program code to: migrate one or more host write commands from the top of the first queue to the second queue in an order of time when the host write commands arrive to the flash controller until the top of the first queue stores a host read command; fetch the host read command from the top of the first queue; execute the host read command to read user data from a flash module; and reply to the host side with the user data.

Abstract: An electronic device with an auxiliary lighting function and an operation method thereof are provided. The electronic device includes a first body, a display screen, and a light-emitting module. The first body has a first surface. The first surface includes a screen area and a border area. The border area surrounds the screen area. The display screen is disposed in the screen area of the first body. The light-emitting module is disposed in the border area of the first body. The light-emitting module provides an illumination light in at least one first area of the border area, and provides an indicating light in at least one second area of the border area.

Abstract: A device includes a multi-layer stack, a channel layer, a ferroelectric layer and buffer layers. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. The ferroelectric layer is disposed between the channel layer and each of the plurality of conductive layers and the plurality of dielectric layers. The buffer layers include a metal oxide, and one of the buffer layers is disposed between the ferroelectric layer and each of the plurality of dielectric layers.

Abstract: A ferroelectric memory device includes a multi-layer stack, a channel layer, a ferroelectric layer and oxygen scavenging layers. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. The ferroelectric layer is disposed between the channel layer and both of the plurality of conductive layers and the plurality of dielectric layers. The oxygen scavenging layers are disposed along sidewalls of the plurality of conductive layer. The plurality of oxygen scavenging layers laterally separate the ferroelectric layer from the plurality of conductive layers.

Abstract: A graphene dispersion includes a graphene and a polyol compound selected from the group consisting of an aromatic polyol represented by Formula (I), and a modified aromatic polyol made by subjecting the aromatic polyol represented by Formula (I) and an epoxidized vegetable oil to a ring opening reaction, wherein p and q are independently integers ranging from 1 to 20. A method for preparing the graphene dispersion, a composition for preparing a polyurethane composite material, and a polyurethane composite material made from the composition are also disclosed.

Abstract: Provided is a ferroelectric memory device having a multi-layer stack disposed over a substrate and including a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A plurality of ferroelectric portions are discretely disposed between the channel layer and the plurality of conductive layers. The plurality of ferroelectric portions are vertically separated from one another by one or more non-zero distances.

Abstract: A ferroelectric memory device includes a multi-layer stack, a channel layer and a III-V based ferroelectric layer. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers of the multi-layer stack. The III-V based ferroelectric layer is disposed between the channel layer and the multi-layer stack, and includes at least one element selected from Group III elements, at least one element selected from Group V elements, and at least one element selected from transition metal elements.

Abstract: A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

Abstract: A method of forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, the first layer stack and the second layer stack having a same layered structure that includes a dielectric material, a channel material over the dielectric material, and a source/drain material over the channel material; forming openings that extend through the first layer stack and the second layer stack; forming inner spacers by replacing portions of the source/drain material exposed by the openings with a first dielectric material; lining sidewalls of the openings with a ferroelectric material; forming gate electrodes by filling the openings with an electrically conductive material; forming a recess through the first layer stack and the second layer stack, the recess extending from a sidewall of the second layer stack toward the gate electrodes; and filling the recess with a second dielectric material.

Abstract: A process of forming a three-dimensional (3D) memory array includes forming a stack having a plurality of conductive layers of carbon-based material separated by dielectric layers. Etching trenches in the stack divides the conductive layers into conductive strips. The resulting structure includes a two-dimensional array of horizontal conductive strips. Memory cells may be distributed along the length of each strip to provide a 3D array. The conductive strips together with additional conductive structure that may have a vertical or horizontal orientation allow the memory cells to be addressed individually. Forming the conductive layers with carbon-based material facilitate etching the trenches to a high aspect ratio. Accordingly, forming the conductive layers of carbon-based material enables the memory array to have more layers or to have a higher area density.

Abstract: A method for forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, wherein each of the first and the second layer stacks comprises a dielectric layer, a channel layer, and a source/drain layer formed successively over the substrate; forming openings that extends through the first layer stack and the second layer stack, where the openings includes first openings within boundaries of the first and the second layer stacks, and a second opening extending from a sidewall of the second layer stack toward the first openings; forming inner spacers by replacing portions of the source/drain layer exposed by the openings with a dielectric material; lining sidewalls of the openings with a ferroelectric material; and forming first gate electrodes in the first openings and a dummy gate electrode in the second opening by filling the openings with an electrically conductive material.

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor comprising: a ferroelectric (FE) material contacting a word line, the FE material being a hafnium-comprising compound, and the hafnium-comprising compound comprising a rare earth metal; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line.

Abstract: Embodiments include structures and methods for fabricating an MFM capacitor having a plurality of metal contacts. An embodiment may include a first metal strip, disposed on a substrate and extending in a first direction, a ferroelectric blanket layer, disposed on the first metal strip, a second metal strip, disposed on the ferroelectric blanket layer and extending in a second direction different from the first direction, and a plurality of metal contacts disposed between the first metal strip and the second metal strip and located within an intersection region of the first metal strip and the second metal strip.

Abstract: A gaming device including a self-stabilizing module with at least two self-stabilizing axes, a display assembled to the self-stabilizing module, a controller assembly assembled to the self-stabilizing module, a motion sensor, and a processing module is provided. A relative movement of the controller assembly and the display are generated via at least one self-stabilizing axis of the self-stabilizing module. The processing module generates a frame signal to transfer to the display according to a program. When the self-stabilizing module is activated and the relative movement is generated, the motion sensor generates a control signal to the processing module, and the processing module generate another frame signal, which correspondingly depicts a posture of the controller assembly relative to the display, to transfer to the display according to the control signal and the program. A gaming controller is also provided.

Abstract: A fan and a balance ring for the fan are provided. The fan includes a housing, a hub disposed in the housing, blades connected to the side surface of the hub, and a balance ring connected to the hub. The balance ring includes a ring chamber and a balance liquid filled in the ring chamber. The volume of the balance liquid is less than the volume of the ring chamber.

Abstract: Methods of manufacturing redistribution circuit structures are disclosed and one of the methods includes the following steps. A seed layer is formed over a die and an encapsulant encapsulating the die. A photoresist material is formed over the seed layer. The photoresist material is exposed through a phase shift mask to an I-line wavelength within an I-line stepper using a numerical aperture equal to or less than 0.18. The photoresist material is developed to form a photoresist layer including photoresist patterns and openings therebetween. A conductive material is formed in the openings. The photoresist patterns are removed to form conductive patterns. By using the conductive patterns as a mask, the seed layer is partially removed, to form seed layer patterns under the conductive patterns, wherein redistribution conductive patterns include the seed layer patterns and the conductive patterns respectively.