Patents by Inventor Chun Chieh

Chun Chieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • IDENTIFYING RELEVANT IMAGING EXAMINATION RECOMMENDATIONS FOR A PATIENT FROM PRIOR MEDICAL REPORTS OF THE PATIENT TO FACILITATE DETERMINING A FOLLOW UP IMAGING EXAMINATION(S) FOR THE PATIENT
    Publication number: 20140288970
    Abstract: A method for identifying relevant follow-up recommendations from medical reports includes identifying with a processor follow-up recommendations in electronically formatted prior medical reports, and visually presenting, via a display monitor, the identified follow-up recommendations. A computing apparatus (102) including a processor that obtains, in electronic format, an imaging examination order for a follow-up imaging examination of a patient, wherein the imaging examination order at least includes a unique identification of the patient, retrieves electronically formatted prior medical reports of the patient from a data repository based on the patient or the unique identification of the patient, identifies follow-up imaging recommendations in the retrieved electronically formatted prior medical reports, and visually presents the identified follow-up imaging recommendations.
    Type: Application
    Filed: March 20, 2014
    Publication date: September 25, 2014
    Applicant: KONINKLIJKE PHILIPS N.V.
    Inventors: Michael Chun-chieh Lee, Yuechen Qian, James Chi-Kuei Shaw
  • Cu pillar bump with non-metal sidewall protection structure
    Patent number: 8841766
    Abstract: Sidewall protection processes are provided for Cu pillar bump technology, in which a protection structure on the sidewalls of the Cu pillar bump is formed of at least one of non-metal material layers, for example a dielectric material layer, a polymer material layer, or combinations thereof.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: September 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Yi-Wen Wu, Chun-Chieh Wang, Chung-Shi Liu
  • Socket with an assembling and unloading mechanism
    Patent number: 8840427
    Abstract: A socket with an assembling and unloading mechanism comprises: a frame, having at least one installing hole; at least one holding member for assembling and unloading the frame and having a plate member and a pair of flexible clamping members disposed on the two sides of the plate member, the plate member has an accepting hole, each of the flexible clamping members has a pressing portion and a hook disposed on the one side of the pressing portion and driven by the pressing portion, each hook buckles the peripheral of the frame adjacent to the installing hole; and at least one connecting port, connecting to the inside of the accepting hole; wherein the hook is unloaded from the frame while pressing the pressing portion, and the holding member is withdrawn from the installing hole.
    Type: Grant
    Filed: December 30, 2012
    Date of Patent: September 23, 2014
    Assignee: YFC-Boneagle Electric Co., Ltd.
    Inventors: Ying-Ming Ku, Chun-Chieh Chen
  • Connector apparatus and adapter apparatus with indication function
    Patent number: 8840425
    Abstract: A connector apparatus with indication function includes a first power line, a current-detecting resistor, a second power line, a ground line, a current-detecting unit, a first voltage comparator, a second voltage comparator, a first light-emitting unit, a second light-emitting unit, and a voltage division unit. The first light-emitting unit is lighting but the second light-emitting unit is not lighting when one side of the connector apparatus is connected to a computer and the other side of the connector apparatus is not connected to a smart 3C electronic product. The first light-emitting unit is not lighting but the second light-emitting unit is lighting when one side of the connector apparatus is connected to a computer and the other side of the connector apparatus is connected to a smart 3C electronic product.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: September 23, 2014
    Assignee: YFC-Boneagle Electric Co., Ltd.
    Inventors: Ying-Ming Ku, Chun-Chieh Chen, Shun-Fa Hung
  • INTEGRATED CIRCUIT STRUCTURE AND FORMATION
    Publication number: 20140264864
    Abstract: One or more integrated circuit structures and techniques for forming such integrated circuit structures are provided. The integrated circuit structures comprise a conductive structure that is formed within a trench in a dielectric layer on a substrate. The conductive structure is formed over a barrier layer formed within the trench, or the conductive structure is formed over a liner formed over the barrier layer. At least some of the dielectric layer, the barrier layer, the liner and the conductive structure are removed, for example, by chemical mechanical polishing, such that a step height exists between a top surface of the substrate and a top surface of the dielectric layer. Removing these layers in this manner removes areas where undesired interlayer peeling is likely to occur. A conductive cap is formed on the conductive structure.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Inventors: Cheng-Hui Weng, Chun-Chieh Lin, Hung-Wen Su
  • Interconnect Sructure for Stacked Device and Method
    Publication number: 20140264682
    Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.
    Type: Application
    Filed: May 21, 2013
    Publication date: September 18, 2014
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Tzu-Hsuan Hsu, Shu-Ting Tsai, Min-Feng Kao
  • MEMS DEVICE STRUCTURE WITH A CAPPING STRUCTURE
    Publication number: 20140264475
    Abstract: An integrated circuit device includes a dielectric layer disposed over a semiconductor substrate, the dielectric layer having a sacrificial cavity formed therein, a membrane layer formed onto the dielectric layer, and a capping structure formed on the membrane layer such that a second cavity is formed, the second cavity being connected to the sacrificial cavity though a via formed into the membrane layer.
    Type: Application
    Filed: June 24, 2013
    Publication date: September 18, 2014
    Inventors: Rueijer Lin, Chun-Chieh Lin, Hung-Wen Su, Minghsing Tsai
  • PIXEL OF A DISPLAY PANEL AND DRIVING METHOD THEREOF
    Publication number: 20140267468
    Abstract: A pixel of a display panel includes a first transistor with a first end coupled to a data line, a control end coupled to a scan line; a second transistor with a first end coupled to a first voltage source, a control end coupled to a second end of the first transistor; a third transistor with a first end coupled to a second end of the second transistor, a control end for receiving a control signal; a light emitting unit with a first end coupled to the second end of the second transistor, a second end coupled to a second voltage source; a first capacitor with a first end coupled to the second end of the first transistor, a second end coupled to a second end of the third transistor; and a second capacitor coupled between the second end of the first capacitor and the second voltage source.
    Type: Application
    Filed: June 27, 2013
    Publication date: September 18, 2014
    Inventors: Chun-Chieh Lin, Ya-Ling Chen
  • Imaging Sensor Structure and Method
    Publication number: 20140264683
    Abstract: The present disclosure provides an embodiment of a method for fabricating a three dimensional (3D) image sensor structure. The method includes providing to an image sensor substrate having image sensors formed therein and a first interconnect structure formed thereon, and a logic substrate having a logic circuit formed therein and a first interconnect structure formed thereon; bonding the logic substrate to the image sensor substrate in a configuration that the first and second interconnect structures are sandwiched between the logic substrate and the image sensor substrate; and forming a conductive feature extending from the logic substrate to the first interconnect structure, thereby electrically coupling the logic circuit to the image sensors.
    Type: Application
    Filed: December 30, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Feng-Chi Hung, Shu-Ting Tsai, Jeng-Shyan Lin, Shuang-Ji Tsai, Wen-I Hsu
  • Stress-Controlled Formation of Tin Hard Mask
    Publication number: 20140273470
    Abstract: Disclosed is a method to form a titanium nitride (TiN) hard mask in the Damascene process of forming interconnects during the fabrication of a semiconductor device, while the type and magnitude of stress carried by the TiN hard mask is controlled. The TiN hard mask is formed in a multi-layered structure where each sub-layer is formed successively by repeating a cycle of processes comprising TiN and chlorine PECVD deposition, and N2/H2 plasma gas treatment. During its formation, the stress to be carried by the TiN hard mask is controlled by controlling the number of TiN sub-layers and the plasma gas treatment duration such that the stress may counter-balance predetermined external stress anticipated on a conventionally made TiN hard mask, which causes trench sidewall distortion, trench opening shrinkage, and gap filling problem.
    Type: Application
    Filed: June 24, 2013
    Publication date: September 18, 2014
    Inventors: Rueijer Lin, Chun-Chieh Lin, Hung-Wen Su, Minghsing Tsai
  • Method and Apparatus for Low Resistance Image Sensor Contact
    Publication number: 20140264504
    Abstract: A method and apparatus for a low resistance image sensor contact, the apparatus comprising a photosensor disposed in a substrate, a first ground well disposed in a first region of the substrate, the first ground well having a resistance lower than the substrate, and a ground line disposed in a region adjacent to the first ground well. The first ground well is configured to provide a low resistance path to the ground line from the substrate for excess free carriers in the first region of the substrate. The apparatus may optionally comprise a second ground well having a lower resistance than the first ground well and disposed between the first ground well and the ground line, and may further optionally comprise a third ground well having a lower resistance than the second ground well and disposed between the second ground well and the ground line.
    Type: Application
    Filed: May 9, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Chun-Chieh Chuang, Shuang-Ji Tsai, Jeng-Shyan Lin
  • Structure and Method for 3D Image Sensor
    Publication number: 20140264508
    Abstract: The present disclosure provides an embodiment of an image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.
    Type: Application
    Filed: December 30, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Feng-Chi Hung, Shuang-Ji Tsai, Jeng-Shyan Lin, Shu-Ting Tsai, Wen-I Hsu
  • Interconnect Structure and Method of Forming Same
    Publication number: 20140264883
    Abstract: A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.
    Type: Application
    Filed: April 19, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung
  • SENSOR ON SIDE OF COMPUTING DEVICE
    Publication number: 20140253439
    Abstract: In one implementation, a housing has a first surface and a second surface. A first side may be between the first surface and the second surface. An input device on may be on the first surface. A sensor on the first side may generate data representing an object detected by the sensor. A controller may process the data and control movement of the cursor on a display when the controller determines that the object is in the shape of a hand in a grip form.
    Type: Application
    Filed: March 7, 2013
    Publication date: September 11, 2014
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Chun-Chieh Chen, James M. Mann
  • THIN FILM APPARATUS
    Publication number: 20140252362
    Abstract: A thin film apparatus having a plurality of thin film cells is disclosed. Each thin film cell includes a crystalline layer and a surrounding layer. The crystalline layer has a shape of polygon. The surrounding layer is partially located on the crystalline layer. The crystalline layer is surrounded by the surrounding layer.
    Type: Application
    Filed: March 7, 2014
    Publication date: September 11, 2014
    Applicant: SenseTech Co., Ltd
    Inventors: Po-Wei LU, Mao-Chen LIU, Wen-Chieh CHOU, Chun-Chieh WANG, Shu-Yi WENG
  • MEMS APPARATUS
    Publication number: 20140252511
    Abstract: A MEMS apparatus includes a pillar, a supporter, and a solder. The pillar has a first side and a second side opposite to the first side. The supporter supports the pillar. The supporter is adjacent to the pillar, but the supporter is not connected to the pillar. The supporter has a third side and a fourth side opposite to the third side. The supporter includes a plurality of first confined layers and a plurality of second confined layers. These first confined layers and these second confined layers are overlapped with each other. The second side and the third side are adjacent to each other. The solder is located between the second side and the third side. The solder is also located at the first side and the fourth side. The solder is utilized to combine the pillar and the supporter. The solder also isolates the pillar and the supporter.
    Type: Application
    Filed: March 7, 2014
    Publication date: September 11, 2014
    Applicant: SenseTech Co., Ltd
    Inventors: Mao-Chen LIU, Po-Wei LU, Wen-Chieh CHOU, Shu-Yi WENG, Chun-Chieh WANG
  • SIGNAL BOOSTING APPARATUS AND METHOD OF BOOSTING SIGNALS
    Publication number: 20140252510
    Abstract: A signal boosting apparatus and a method of boosting signals applied in the MEMS are disclosed. The signal boosting apparatus includes a substrate, an oxide layer, and a signal transmission layer. The substrate has a doped region. The doped region has a plurality of conductive carriers. These conductive carriers have the same polarity as an electronic signal. The oxide layer is located on the substrate, and the signal transmission layer is located on the oxide layer. The signal transmission layer can receive and boost the electronic signal.
    Type: Application
    Filed: March 7, 2014
    Publication date: September 11, 2014
    Applicant: SenseTech Co., Ltd
    Inventors: Mao-Chen LIU, Po-Wei LU, Wen-Chieh CHOU, Shu-Yi WENG, Chun-Chieh WANG
  • Backside Structure and Methods for BSI Image Sensors
    Publication number: 20140252523
    Abstract: A back side image sensor and method of manufacture are provided. In an embodiment a bottom anti-reflective coating is formed over a substrate, and a metal shield layer is formed over the bottom anti-reflective coating. The metal shield layer is patterned to form a grid pattern over a sensor array region of the substrate, and a first dielectric layer and a second dielectric layer are formed to at least partially fill in openings within the grid pattern.
    Type: Application
    Filed: May 16, 2014
    Publication date: September 11, 2014
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Wen-De Wang, Keng-Yu Chou, Shuang-Ji Tsai, Min-Feng Kao
  • Image Sensor with Improved Dark Current Performance
    Publication number: 20140252521
    Abstract: Provided is a semiconductor image sensor device. The image sensor device includes a semiconductor substrate having a first side and a second side opposite the first side. The semiconductor substrate contains a radiation-sensing region configured to sense radiation projected toward the substrate from the second side. A first layer is disposed over the second side of the semiconductor substrate. The first layer has a first energy band gap. A second layer is disposed over the first layer. The second layer has a second energy band gap. A third layer is disposed over the second layer. The third layer has a third energy band gap. The second energy band gap is smaller than the first energy band gap and the third energy band gap.
    Type: Application
    Filed: September 18, 2013
    Publication date: September 11, 2014
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Shuang-Ji Tsai, Jeng-Shyan Lin, Chun-Chieh Chuang
  • CMOS Image Sensors and Methods for Forming the Same
    Publication number: 20140248734
    Abstract: A method includes forming a first implantation mask comprising a first opening, implanting a first portion of a semiconductor substrate through the first opening to form a first doped region, forming a second implantation mask comprising a second opening, and implanting a second portion of the semiconductor substrate to form a second doped region. The first portion of the semiconductor substrate is encircled by the second portion of the semiconductor substrate. A surface layer of the semiconductor substrate is implanted to form a third doped region of an opposite conductivity type than the first and the second doped regions. The third doped region forms a diode with the first and the second doped regions.
    Type: Application
    Filed: May 7, 2014
    Publication date: September 4, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Hsiao-Hui Tseng, Tzu-Hsuan Hsu