Patents by Inventor Chun-Hsien Lin

Chun-Hsien Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210223223
    Abstract: A system and a method for managing and trading fresh foods according to a flavor thereof, comprising a plurality of fresh foods, an image capturing module, a processing module and a classification module. The fresh food is attached with a product label including a code and a colorimetric transducer array that comprises at least one sensing material for sensing the fresh food. The sensing material undergoes a chemical reaction with at least one metabolic molecule of the fresh food to change the sensing material from an initial color to an indication color. The image capturing module captures an image comprising an appearance of the fresh food, the code and the indication color. The processing module provides a real-time information according to a comparison result between the image and a database. The classification module receives the real-time information and classifies the fresh food according to the real-time information.
    Type: Application
    Filed: January 6, 2021
    Publication date: July 22, 2021
    Inventors: Ching-Tung HSU, Chun-Wei SHIH, Chao-Chieh LIN, Yuan-Shin HUANG, Chia-Hung LI, Chun-Hsien TSAI, Chun-Jung TSAI
  • Publication number: 20210220964
    Abstract: A chemical mechanical planarization apparatus includes a multi-zone platen comprising a plurality of individually controlled concentric toroids. The rotation direction, rotation speed, applied force, relative height, and temperature of each concentric toroid is individually controlled. Concentric polishing pads are affixed to an upper surface of each of the individually controlled concentric toroids. The chemical mechanical planarization apparatus includes a single central slurry source or includes individual slurry sources for each individually controlled concentric toroid.
    Type: Application
    Filed: January 17, 2020
    Publication date: July 22, 2021
    Inventors: Ting-Hsun Chang, Hung Yen, Chi-Hsiang Shen, Fu-Ming Huang, Chun-Chieh Lin, Tsung Hsien Chang, Ji Cui, Liang-Guang Chen, Chih Hung Chen, Kei-Wei Chen
  • Publication number: 20210219435
    Abstract: A circuit carrier board includes a first build-up layer structure, a substrate, an adhesive layer, and a conductive structure. The first build-up layer includes a plurality of first dielectric layers and a plurality of first circuit layers original stacked. The substrate includes a base and a second build-up layer structure disposed on the base. The second build-up layer structure includes a plurality of second dielectric layers and a plurality of second circuit layer original stacked. A top most layer of the second circuit layers is exposed outside of the second dielectric layers. The conductive structure penetrates through the first dielectric layers, the first circuit layers and the adhesive layer, and contacts with the top most layer of the second circuit layers. The conductive structure electrical connects the first circuit layers to the second circuit layers. A manufacturing method of the circuit carrier board is also provided.
    Type: Application
    Filed: April 1, 2021
    Publication date: July 15, 2021
    Applicant: Unimicron Technology Corp.
    Inventors: Chun-Hsien Chien, Wen-Liang Yeh, Wei-Ti Lin
  • Publication number: 20210216826
    Abstract: A model training method and an electronic device are provided. The method includes the following steps: establishing a brain age prediction model according to a training set; adjusting a parameter in the brain age prediction model according to a validation set; inputting a test set into the brain age prediction model with the adjusted parameter to obtain a plurality of first predicted brain ages; determining whether the first predicted brain ages satisfy a first specific condition; and completing training of the brain age prediction model when the first predicted brain ages satisfy the first specific condition.
    Type: Application
    Filed: March 27, 2020
    Publication date: July 15, 2021
    Applicants: Acer Incorporated, National Yang-Ming University
    Inventors: Cheng-Tien Hsieh, Chun-Hsien Yu, Shih-Ho Huang, Meng-Che Cheng, Kun-Hsien Chou, Ching-Po Lin, Liang-Kung Chen
  • Publication number: 20210210675
    Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, an inter-metal dielectric (IMD) layer on the substrate, a MTJ in the IMD layer on the MTJ region, a first metal interconnection in the IMD layer on the logic region, and protrusions adjacent to two sides of the first metal interconnection. Preferably, the MTJ further includes a bottom electrode, a fixed layer, a barrier layer, a free layer, and a top electrode.
    Type: Application
    Filed: March 23, 2021
    Publication date: July 8, 2021
    Inventors: An-Chi Liu, Chun-Hsien Lin
  • Patent number: 11017241
    Abstract: A people-flow analysis system includes an image source, a computing device, and a host. The image source captures a first image and a second image. The computing device is connected to the image source. The computing device identifies the first image according to a data set to generate a first detecting image. The first detecting image has a position box corresponding to a pedestrian in the first image. The computing device generates a tracking image according to the data set and a difference between the first detecting image and the second image. The tracking image has another position box corresponding to a pedestrian in the second image. The host is connected to the computing device and generates a people-flow list according to the first detecting image and the tracking image.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: May 25, 2021
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Bing-Fei Wu, Chun-Hsien Lin, Po-Wei Huang, Meng-Liang Chung
  • Patent number: 11004753
    Abstract: A display device includes a substrate, a light-emitting element, and a transistor. The substrate has a top surface. The light-emitting element is disposed on the substrate. The transistor is disposed on the substrate, and includes a drain electrode, a gate electrode, and a semiconductor layer. The drain electrode is electrically connected to the light-emitting element. The semiconductor layer includes an overlapping portion overlapped with the gate electrode. The light-emitting element does not overlap with the overlapping portion along a direction perpendicular to the top surface of the substrate.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: May 11, 2021
    Assignee: INNOLUX CORPORATION
    Inventors: Tung-Kai Liu, Tsau-Hua Hsieh, Wei-Cheng Chu, Chun-Hsien Lin, Chandra Lius, Ting-Kai Hung, Kuan-Feng Lee, Ming-Chang Lin, Tzu-Min Yan, Hui-Chieh Wang
  • Patent number: 10991875
    Abstract: A semiconductor device includes: a substrate having a magnetic tunneling junction (MTJ) region and a logic region; an inter-metal dielectric (IMD) layer on the substrate; a first metal interconnection in the IMD layer on the logic region; and protrusions adjacent to two sides of the first metal interconnection. Preferably, the first metal interconnection further includes a via conductor and a trench conductor and the protrusions includes a first protrusion on one side of the via conductor and a second protrusion on another side of the via conductor.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: April 27, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: An-Chi Liu, Chun-Hsien Lin
  • Publication number: 20210118750
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.
    Type: Application
    Filed: December 27, 2020
    Publication date: April 22, 2021
    Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
  • Publication number: 20210083073
    Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a gate electrode on the barrier layer, a first passivation layer adjacent to two sides of the gate electrode, and a p-type semiconductor layer between the gate electrode and the barrier layer. Preferably, a corner of the p-type semiconductor layer contacting a sidewall of the first passivation layer includes a first curve, and a bottom surface of the p-type semiconductor layer directly on the first passivation layer includes a second curve.
    Type: Application
    Filed: October 14, 2019
    Publication date: March 18, 2021
    Inventors: An-Chi Liu, Chun-Hsien Lin
  • Patent number: 10951163
    Abstract: A smart method is provided for a low-current oscillatory circuitry. The circuitry comprises an oscillator and a microcontroller unit (MCU). The oscillator comprises a proportional-to-absolute-temperature circuit connecting to a low-voltage regulator. The low-voltage regulator connects to a PMOS diode array and a delay unit circuit. The PMOS diode array connects to the MCU. The delay unit circuit connects to the MCU and a voltage converter. The method includes a normal temperature compensation algorithm; a smart learning algorithm of extra-high temperature compensation; and an ultra-high temperature compensation algorithm. Thus, clock variations are compensated; output frequency is stable and not affected by voltage or temperature variations; and process variations are suppressed. When process variations appear, there are not be too many errors generated.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: March 16, 2021
    Assignees: Dyna Image Corporation, Lite-On Semiconductor Corp.
    Inventors: Sheng-Cheng Lee, Wen-Sheng Lin, Yu-Cheng Su, Chun-Hsien Lin, Peng-Han Chan
  • Patent number: 10937775
    Abstract: Provided is a display device, which includes a substrate, a transistor, a capacitor and a light emitting unit. The transistor and the capacitor are disposed on the substrate. The light emitting unit is disposed on the substrate and arranged corresponding to the capacitor. The light emitting unit includes a first light emitting diode. The first light emitting diode is electrically connected with the transistor and overlaps the capacitor. The display device has favorable space utilization, provides a repair function, or reduces the probability of failure.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: March 2, 2021
    Assignee: Innolux Corporation
    Inventors: Chun-Hsien Lin, Shun-Yuan Hu, Tsau-Hua Hsieh, Li-Wei Mao, Tung-Kai Liu, Shu-Ming Kuo, Chih-Yung Hsieh
  • Publication number: 20210057551
    Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.
    Type: Application
    Filed: November 6, 2020
    Publication date: February 25, 2021
    Inventors: Po-Chang Lin, Bo-Han Huang, Chih-Chung Chen, Chun-Hsien Lin, Shih-Hung Tsai, Po-Kuang Hsieh
  • Publication number: 20210043632
    Abstract: A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a first doped region in a substrate; removing part of the first doped region to form a trench in the substrate; forming a gate structure in the trench; and forming a barrier structure between the gate structure and the first doped region.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 11, 2021
    Inventors: Feng-Yi Chang, Chun-Hsien Lin, Fu-Che Lee
  • Patent number: 10915079
    Abstract: A light sensor device is provided. It is controlled with a dual-mode master-and-slave microcontroller unit (MCU) application. An MCU is embedded into a light sensor chip. The original dual-mode master-and-slave dual-CPU architectures are combined to be operated as a single-CPU architecture. Since the original circuit pin design is followed, it is possible to be compatible with the old circuit design. The present invention uses a single-CPU architecture to directly control light sensors. Through the configuration of RAM, an inter-integrated circuit bus (I2C I/F) can be redirected to an internal non-volatile memory to switch the operational mode of the light sensor chip from a slave machine to a host machine which switches off the interrupt pin and, then, turns to a GPIO pin. Thus, the present invention provides a simple single-CPU architecture with easy use and effectively-lowered cost.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: February 9, 2021
    Assignees: Dyna Image Corporation, Lite-On Semiconductor Corporation
    Inventors: Chun-Hsien Lin, Peng-Han Chan, Wen-Sheng Lin, Yu-Cheng Su, Sheng-Cheng Lee
  • Patent number: 10909914
    Abstract: A semiconductor device includes a first display unit and a second display unit. The first display unit includes a first substrate, first light-emitting units, and a first gate driver circuit. The first substrate includes a first display region. The first substrate has a first side and a second side. The first light-emitting units are disposed in the first display region. The first gate driver circuit is disposed in the first display region. The second display unit is adjacent to the first display unit. The second display unit includes a second substrate. The second substrate includes a second display region, second light-emitting units, and a second gate driver circuit. The second substrate has a third side and a fourth side. The second light-emitting units are disposed in the second display region. A second gate driver circuit is disposed in the second display region.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: February 2, 2021
    Assignee: INNOLUX CORPORATION
    Inventors: Geng-Fu Chang, Jui-Feng Ko, Tsau-Hua Hsieh, Chun-Hsien Lin, Jian-Jung Shih
  • Patent number: 10910277
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: February 2, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
  • Patent number: 10886395
    Abstract: A method for fabricating a tunnel field effect transistor (TFET) includes the steps of providing a substrate and then forming an interfacial layer on the substrate. Preferably, the step of forming the interfacial layer includes the steps of: performing a plasma treatment process to inject a first gas containing nitrogen; injecting a second gas containing oxygen; and injecting a precursor to react with the first gas and the second gas for forming the interfacial layer.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: January 5, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: An-Chi Liu, Chun-Hsien Lin
  • Patent number: 10868148
    Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: December 15, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Chang Lin, Bo-Han Huang, Chih-Chung Chen, Chun-Hsien Lin, Shih-Hung Tsai, Po-Kuang Hsieh
  • Publication number: 20200381615
    Abstract: A semiconductor device includes: a substrate having a magnetic tunneling junction (MTJ) region and a logic region; an inter-metal dielectric (IMD) layer on the substrate; a first metal interconnection in the IMD layer on the logic region; and protrusions adjacent to two sides of the first metal interconnection. Preferably, the first metal interconnection further includes a via conductor and a trench conductor and the protrusions includes a first protrusion on one side of the via conductor and a second protrusion on another side of the via conductor.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 3, 2020
    Inventors: An-Chi Liu, Chun-Hsien Lin