Abstract: An electronic device is provided. The electronic device includes a substrate, an electronic unit, and a circuit layer. The substrate has a first surface and a second surface, and the second surface is opposite the first surface. The electronic unit is disposed on the first surface. The circuit layer is disposed on the second surface. The circuit layer includes a plurality of first wirings and a plurality of second wirings. The plurality of first wirings are used to transmit a first signal. The plurality of second wirings are used to transmit a second signal. Moreover, a width of one of the plurality of second wirings is different from a width of one of the plurality of first wirings.

Abstract: A nanowire transistor includes a channel structure on a substrate, a gate structure on and around the channel structure, a source/drain structure adjacent to two sides of the gate structure, and a contact plug connected to the source/drain structure. Preferably, the source/drain structure includes graphene and the contact plug further includes a silicide layer on the source/drain structure, a graphene layer on the silicide layer, and a barrier layer on the graphene layer.

Abstract: The invention provides a semiconductor layout pattern including high-voltage devices, which comprises a substrate, wherein a high-voltage device region and an MRAM (magnetic random access memory) region are adjacent to each other, wherein the MRAM region at least comprises a plurality of MRAM cells arranged in an array, wherein each MRAM cell comprises two fin structures parallel to each other and arranged along an X direction, and two gate structures parallel to each other and arranged along a Y direction. A drain metal layer is located between the two gate structures, two source metal layers are located on the other side of the two gate structures, respectively, and an MTJ (magnetic tunneling junction) element is electrically connected with the drain metal layers.

Abstract: A method for fabricating semiconductor device includes the steps of providing a substrate having a first region and a second region, forming a first fin-shaped structure on the first region, removing part of the first fin-shaped structure to form a first trench, forming a dielectric layer in the first trench to form a double diffusion break (DDB) structure, forming a first gate structure and a second gate structure on the DDB structure as a bottom surface of the first gate structure is lower than a top surface of the first fin-shaped structure, and forming a contact plug between the first gate structure and the second gate structure on the DDB structure.

Abstract: An electronic device includes a first substrate, a second substrate, organic light emitting diodes, a filter layer, a third substrate, a structure, and a first adhesive element. At least a part of the organic light emitting diodes are disposed on the first substrate. The filter layer is disposed at least on the second substrate. The third substrate is disposed corresponding to the first substrate and the second substrate. The organic light emitting diodes and the structure are disposed under the third substrate. The first adhesive element is disposed between the first substrate and the second substrate, directly contacts the structure, and does not overlap with the organic light emitting diodes. A distance between a bottom surface of the structure and a top surface of the third substrate is different from a minimum distance between one of the organic light emitting diodes and the top surface of the third substrate.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a fin-shaped structure on a substrate, forming a gate material layer on the fin-shaped structure, performing an etching process to pattern the gate material layer for forming a gate structure and a silicon residue, performing an ashing process on the silicon residue, and then performing a cleaning process to transform the silicon residue into a polymer stop layer on a top surface and sidewalls of the fin-shaped structure.

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, an inter-metal dielectric (IMD) layer on the substrate, a MTJ in the IMD layer on the MTJ region, a first metal interconnection in the IMD layer on the logic region, and protrusions adjacent to two sides of the first metal interconnection. Preferably, the MTJ further includes a bottom electrode, a fixed layer, a barrier layer, a free layer, and a top electrode.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region, forming a fin NMOS transistor on the first NMOS region, forming a fin PMOS transistor on the first PMOS region, forming a planar NMOS transistor on the second NMOS region, forming a planar PMOS transistor on the second PMOS region, and forming a planar MOS capacitor on the MOS capacitor region.

Abstract: An electronic device includes a conductive structure, a semiconductor, a first insulation layer and a second insulation layer. The semiconductor is electrically connected to the conductive structure. The first insulation layer is disposed between the conductive structure and the second insulation layer. The first insulation layer includes a first hole, and the first hole overlaps a part of the conductive structure. The second insulation layer includes a second hole, and the first hole and the second hole at least partially overlap. Along a direction, a width of the second hole is less than a width of the first hole.

Abstract: A one-time programmable memory structure includes semiconductor substrate of a first conductivity type and a fin disposed on the semiconductor substrate. The fin extends along a first direction, wherein the fin includes a first portion and a second portion that is contiguous with the first portion. The first portion and the second portion have different cross-sectional profiles. A gate extends on the fin along a second direction. The gate partially overlaps the first portion of the fin and partially overlaps the second portion of the fin.

Abstract: A nanowire transistor includes a channel structure on a substrate, a gate structure on and around the channel structure, a source/drain structure adjacent to two sides of the gate structure, and a contact plug connected to the source/drain structure. Preferably, the source/drain structure includes graphene and the contact plug further includes a silicide layer on the source/drain structure, a graphene layer on the silicide layer, and a barrier layer on the graphene layer.

Abstract: A semiconductor device includes a substrate having a medium-voltage (MV) region and an one time programmable (OTP) capacitor region, a MV device on the MV region, and an OTP capacitor on the OTP capacitor region. Preferably, the MV device includes a first gate dielectric layer on the substrate, a first gate electrode on the first gate dielectric layer, and a shallow trench isolation (STI) adjacent to two sides of the first gate electrode. The OTP capacitor includes a fin-shaped structure on the substrate, a doped region in the fin-shaped structure, a second gate dielectric layer on the doped region, and a second gate electrode on the second gate dielectric layer.

Abstract: A method for fabricating a physically unclonable function (PUF) device includes the steps of first providing a PUF cell array having a plurality of unit cells, in which each of the unit cells includes a transistor and a first metal-oxide semiconductor capacitor (MOSCAP) and a second MOSCAP coupled to the transistor. Next, a voltage is transmitted through the transistor to the first MOSCAP and the second MOSCAP and whether the first MOSCAP or the second MOSCAP reaches a breakdown is determined.

Abstract: A method for fabricating a surface acoustic wave (SAW) device includes the steps of forming a buffer layer on a substrate, forming a high velocity layer on the buffer layer, forming a medium velocity layer on the high velocity layer, forming a low velocity layer on the medium velocity layer, forming a piezoelectric layer on the low velocity layer, and forming an electrode on the piezoelectric layer. Preferably, the buffer layer includes silicon oxide, the high velocity layer includes graphene, the medium velocity layer includes silicon oxynitride, and the low velocity layer includes titanium oxide.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region, forming a fin NMOS transistor on the first NMOS region, forming a fin PMOS transistor on the first PMOS region, forming a planar NMOS transistor on the second NMOS region, forming a planar PMOS transistor on the second PMOS region, and forming a planar MOS capacitor on the MOS capacitor region.

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, an inter-metal dielectric (IMD) layer on the substrate, a MTJ in the IMD layer on the MTJ region, a first metal interconnection in the IMD layer on the logic region, and protrusions adjacent to two sides of the first metal interconnection. Preferably, the MTJ further includes a bottom electrode, a fixed layer, a barrier layer, a free layer, and a top electrode.

Abstract: An electronic device includes a substrate including a first surface and a second surface opposite to the first surface; a first data line and a second data line disposed on the first surface of the substrate and extending along a first direction; a first electronic unit disposed on the first surface of the substrate; a first control unit disposed on the first surface of the substrate; a first scan line crossing the first data line and the second data line, wherein the first control unit is electrically connected between the first electronic unit and the first scan line; a first switch element disposed on the first surface of the substrate, and comprising a first gate; a first conductive pad disposed on the second surface of the substrate; and a first signal line electrically connected between the first gate of the first switch element and the first conductive pad.

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first fin-shaped structure extending along a first direction on the first region, a double diffusion break (DDB) structure extending along a second direction to divide the first fin-shaped structure into a first portion and a second portion, and a first gate structure and a second gate structure extending along the second direction on the DDB structure.

Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.

Abstract: An electronic device includes a substrate, a circuit structure, a light blocking layer and an opening. The circuit structure is disposed on the substrate and includes at least one data wire, at least one scan wire, a plurality of primary bonding pads, and a plurality of reserved bonding pads. The plurality of primary bonding pads are configured to be bonded with electronic elements, and the plurality of reserved bonding pads are configured to be bonded with repair or backup electronic elements. The light blocking layer is disposed on the substrate and overlapping with the circuit structure. A material of the light blocking layer includes metal. The opening is surrounded and enclosed by the light blocking layer, and configured to allow ambient light to penetrate. The opening does not overlap with the plurality of primary bonding pads and the plurality of reserved bonding pads.