Patents by Inventor Chun-Hsien Lin

Chun-Hsien Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240098932
    Abstract: A foldable electronic device, including a first body, a second body, an air valve movably disposed in the first body, at least one triggering member, and a hinge connecting the first body and the second body, is provided. The first body has multiple openings respectively located at two opposite surfaces. The triggering member is movably disposed in the first body and has a part exposed outside the first body. The air valve and the triggering member are mutually on moving paths of each other. The first body and the second body are rotated to be folded or unfolded relative to each other by the hinge. A part of the triggering member is suitable for bearing a force such that the triggering member drives the air valve, so that the air valve opens or closes the openings.
    Type: Application
    Filed: July 19, 2023
    Publication date: March 21, 2024
    Applicant: Acer Incorporated
    Inventors: Hui-Ping Sun, Jui-Yi Yu, Chun-Hung Wen, Yen-Chou Chueh, Yu-Ming Lin, Chun-Hsien Chen
  • Publication number: 20240096907
    Abstract: An electronic device is provided. The electronic device includes a substrate, an electronic unit, and a circuit layer. The substrate has a first surface and a second surface, and the second surface is opposite the first surface. The electronic unit is disposed on the first surface. The circuit layer is disposed on the second surface. The circuit layer includes a plurality of first wirings and a plurality of second wirings. The plurality of first wirings are used to transmit a first signal. The plurality of second wirings are used to transmit a second signal. Moreover, a width of one of the plurality of second wirings is different from a width of one of the plurality of first wirings.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventor: Chun-Hsien LIN
  • Patent number: 11935728
    Abstract: In order to reduce the occurrence of current alarms in a semiconductor etching or deposition process, a controller determines an offset in relative positions of a cover ring and a shield over a wafer within a vacuum chamber. The controller provides a position alarm and/or adjusts the position of the cover ring or shield when the offset is greater than a predetermined value or outside a range of acceptable values.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Cheng Wu, Sheng-Ying Wu, Ming-Hsien Lin, Chun Fu Chen
  • Publication number: 20240074329
    Abstract: The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a first interconnect layer and a second interconnect layer. The first interconnect layer is disposed on the substrate, and the first interconnect layer includes a first dielectric layer around a plurality of first magnetic tunneling junction (MTJ) structures. The second interconnect layer is disposed on the first interconnect layer, and the second interconnect layer includes a second dielectric layer around a plurality of second MTJ structures, wherein, the second MTJ structures and the first MTJ structures are alternately arranged along a direction. The semiconductor device may obtain a reduced size of each bit cell under a permissible process window, so as to improve the integration of components.
    Type: Application
    Filed: November 8, 2023
    Publication date: February 29, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Hsing Lee, Chun-Hsien Lin, Sheng-Yuan Hsueh
  • Patent number: 11916314
    Abstract: A mobile device includes a housing, a first radiation element, a second radiation element, a third radiation element, a first switch element, and a second switch element. The first radiation element has a first feeding point. The second radiation element has a second feeding point. The first radiation element, the second radiation element, and the third radiation element are distributed over the housing. The first switch element is closed or open, so as to selectively couple the first radiation element to the third radiation element. The second switch element is closed or open, so as to selectively couple the second radiation element to the third radiation element. An antenna structure is formed by the first radiation element, the second radiation element, and the third radiation element.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: February 27, 2024
    Assignee: HTC Corporation
    Inventors: Cheng-Hung Lin, Szu-Po Wang, Chia-Te Chien, Chun-Chieh Wang, Kang-Ling Li, Chun-Hsien Lee, Yu-Chieh Chiu
  • Patent number: 11914804
    Abstract: A touch display device is provided in this disclosure. The touch display device includes a substrate, a first conductive layer, a second conductive layer, a stacked structure, an inorganic light emitting unit, and a touch sensing circuit. The first conductive layer is disposed on the substrate. The first conductive layer includes a gate electrode. The second conductive layer is disposed on the first conductive layer. The second conductive layer includes a source electrode and a drain electrode. The stacked structure is disposed on the substrate. The stacked structure includes a conductive channel and a sensing electrode. The inorganic light emitting unit is disposed on the stacked structure. The inorganic light emitting unit is electrically connected with the drain electrode via the conductive channel. The touch sensing circuit is electrically connected with the sensing electrode.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: February 27, 2024
    Assignee: InnoLux Corporation
    Inventors: Po-Yang Chen, Hsing-Yuan Hsu, Tzu-Min Yan, Chun-Hsien Lin, Kuei-Sheng Chang
  • Publication number: 20240062713
    Abstract: An electronic device includes a substrate, a transistor, a first conductive portion, a first power input portion and a first wire. The substrate includes a first surface, a second surface opposite to the first surface, and a side surface located between the first surface and the second surface. The transistor is disposed on the first surface. The first conductive portion is disposed on the side surface and electrically connected to the transistor. The first power input portion and the first wire are disposed on the second surface. The first power input portion is electrically connected to the first conductive portion through the first wire. The first wire includes a first segment, a second segment and a third segment. An extension direction of the first segment, an extension direction of the second segment, and an extension direction of the third segment are not parallel to each other.
    Type: Application
    Filed: October 27, 2023
    Publication date: February 22, 2024
    Applicant: Innolux Corporation
    Inventor: Chun-Hsien Lin
  • Patent number: 11908395
    Abstract: An electronic device including a panel, a Chip on Film and a flexible circuit board is disclosed. The panel includes a first gate driver, a switch transistor and a driving transistor. An output terminal of the switch transistor is coupled to a control terminal of the driving transistor. The first gate driver is used for receiving an AC signal and a DC signal and outputting a control signal to a control terminal of the switch transistor. The Chip on Film is electrically connected to the panel and used for transmitting a data signal to an input terminal of the switch transistor and transmitting the AC signal to the first gate driver. The flexible circuit board is electrically connected to the panel and used for transmitting a power signal to an input terminal of the driving transistor and transmitting the DC signal to the first gate driver.
    Type: Grant
    Filed: February 8, 2023
    Date of Patent: February 20, 2024
    Assignee: InnoLux Corporation
    Inventors: Chun-Hsien Lin, Jui-Feng Ko, Geng-Fu Chang
  • Patent number: 11869900
    Abstract: An electronic device is provided. The electronic device includes a substrate, a light-emitting unit, and a circuit layer. The substrate has a first surface and a second surface, and the second surface is opposite the first surface. The light-emitting unit is disposed on the first surface, and the circuit layer is disposed on the second surface. The circuit layer includes a first layer and a second layer. The second layer is disposed on the first layer. The first layer includes a plurality of first wirings. The second layer includes a plurality of second wirings. The plurality of first wirings intersect with the plurality of second wirings.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: January 9, 2024
    Assignee: INNOLUX CORPORATION
    Inventor: Chun-Hsien Lin
  • Publication number: 20240006468
    Abstract: A method for fabricating a resistor structure includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, patterning the p-type semiconductor layer, trimming the barrier layer along a first direction, and then forming an electrode on the barrier layer along a second direction.
    Type: Application
    Filed: July 28, 2022
    Publication date: January 4, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Hsing Lee, Chun-Hsien Lin, Chih-Wei Yang
  • Publication number: 20240006405
    Abstract: The invention provides a semiconductor structure, which comprises a first standard cell and a second standard cell located on a substrate, wherein an isolation region is included between the first standard cell and the second standard cell, a plurality of fin structures and a plurality of gates form a plurality of transistors, which are respectively located in the first standard cell and the second standard cell, and a plurality of single diffusion breaks (SDBs) located in the first standard cell and the second standard cell. A plurality of first dummy grooves in the first standard cell and the second standard cell, and a plurality of second dummy grooves in the isolation region, wherein some of the second dummy grooves overlap the first dummy grooves.
    Type: Application
    Filed: July 28, 2022
    Publication date: January 4, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hsien Lin, Chien-Hung Chen, Ruei-Yau Chen
  • Patent number: 11862622
    Abstract: An integrated circuit layout includes a first standard cell and a second standard cell. The first standard cell includes first gate lines arranged along a first direction and extending along a second direction. The second standard cell abuts to one side of the first standard cell along the second direction and includes second gate lines arranged along the first direction and extending along the second direction. A first gate line width of the first gate lines and a second gate line width of the second gate lines are different. A first cell width of the first standard cell and a second cell width of the second standard cell are integral multiples of a default gate line pitch of the first gate lines and the second gate lines. At least some of the second gate lines and at least some of the first gate lines are aligned along the second direction.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: January 2, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-Yuan Wu, Wei-Jen Wang, Chien-Fu Chen, Chen-Hsien Hsu, Chien-Hung Chen, Chun-Hsien Lin
  • Publication number: 20230420564
    Abstract: A semiconductor device includes a substrate having a first region and a second region, a first fin-shaped structure extending along a first direction on the first region, a double diffusion break (DDB) structure extending along a second direction to divide the first fin-shaped structure into a first portion and a second portion, and a first gate structure and a second gate structure extending along the second direction on the DDB structure.
    Type: Application
    Filed: September 11, 2023
    Publication date: December 28, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shou-Wan Huang, Chun-Hsien Lin
  • Patent number: 11856867
    Abstract: The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a first interconnect layer and a second interconnect layer. The first interconnect layer is disposed on the substrate, and the first interconnect layer includes a first dielectric layer around a plurality of first magnetic tunneling junction (MTJ) structures. The second interconnect layer is disposed on the first interconnect layer, and the second interconnect layer includes a second dielectric layer around a plurality of second MTJ structures, wherein, the second MTJ structures and the first MTJ structures are alternately arranged along a direction. The semiconductor device may obtain a reduced size of each bit cell under a permissible process window, so as to improve the integration of components.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: December 26, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Hsing Lee, Chun-Hsien Lin, Sheng-Yuan Hsueh
  • Patent number: 11847961
    Abstract: An electronic device includes a substrate, an array circuit, a first distribution terminal, a second distribution terminal, a first power input terminal, a first wire and a second wire. The first distribution terminal and the second distribution terminal are disposed on a side surface of the substrate and are electrically connected to the array circuit. The first power input terminal, the first wire and the second wire are disposed on a bottom surface of the substrate. A first end of the first power input terminal is electrically connected to the first distribution terminals through the first wire. A second end of the first power input terminal opposite to the first end is electrically connected to the second distribution terminals through the second wire. A minimum distance between the first end and the first distribution terminal is less than a minimum distance between the second end and the first distribution terminal.
    Type: Grant
    Filed: November 27, 2022
    Date of Patent: December 19, 2023
    Assignee: Innolux Corporation
    Inventor: Chun-Hsien Lin
  • Publication number: 20230403942
    Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.
    Type: Application
    Filed: August 28, 2023
    Publication date: December 14, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wei Liu, Jia-Feng Fang, Chun-Hsien Lin
  • Publication number: 20230402527
    Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a gate electrode on the barrier layer, a field plate adjacent to two sides of the gate electrode, and a first passivation layer adjacent to two sides of the gate electrode. Preferably, a sidewall of the field plate includes a first curve.
    Type: Application
    Filed: August 28, 2023
    Publication date: December 14, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: An-Chi Liu, Chun-Hsien Lin
  • Publication number: 20230386939
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the first fin-shaped structure into a first portion and a second portion, and more than two gate structures on the SDB structure. Preferably, the more than two gate structures include a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure disposed on the SDB structure.
    Type: Application
    Filed: August 14, 2023
    Publication date: November 30, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
  • Publication number: 20230378166
    Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a resistor region, forming a first gate structure on the resistor region, forming a first interlayer dielectric (ILD) layer around the first gate structure, transforming the first gate structure into a first metal gate having a gate electrode on the substrate and a hard mask on the gate electrode, and then forming a resistor on the first metal gate.
    Type: Application
    Filed: June 20, 2022
    Publication date: November 23, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Hsing Lee, Chun-Hsien Lin, Yung-Chen Chiu, Sheng-Yuan Hsueh, Chi-Horn Pai
  • Publication number: 20230380148
    Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having an one time programmable (OTP) device region, forming a shallow trench isolation (STI) in the substrate, forming a first doped region adjacent to the STI, removing part of the STI, and then forming a first gate structure on the substrate and the STI. Preferably, the first gate structure includes a high-k dielectric layer on the substrate and a gate electrode on the high-k dielectric layer, in which the high-k dielectric layer comprises a first L-shape.
    Type: Application
    Filed: June 20, 2022
    Publication date: November 23, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Hsing Lee, Chun-Hsien Lin, Chih-Kai Kang, Ting-Hsiang Huang, Chien-Liang Wu, Sheng-Yuan Hsueh, Chi-Horn Pai