Abstract: A method for fabricating a physically unclonable function (PUF) device includes the steps of first providing a PUF cell array having a plurality of unit cells, in which each of the unit cells includes a transistor and a first metal-oxide semiconductor capacitor (MOSCAP) and a second MOSCAP coupled to the transistor. Next, a voltage is transmitted through the transistor to the first MOSCAP and the second MOSCAP and whether the first MOSCAP or the second MOSCAP reaches a breakdown is determined.

Abstract: A semiconductor device includes a substrate having a medium-voltage (MV) region and an one time programmable (OTP) capacitor region, a MV device on the MV region, and an OTP capacitor on the OTP capacitor region. Preferably, the MV device includes a first gate dielectric layer on the substrate, a first gate electrode on the first gate dielectric layer, and a shallow trench isolation (STI) adjacent to two sides of the first gate electrode. The OTP capacitor includes a fin-shaped structure on the substrate, a doped region in the fin-shaped structure, a second gate dielectric layer on the doped region, and a second gate electrode on the second gate dielectric layer.

Abstract: A method for fabricating a surface acoustic wave (SAW) device includes the steps of forming a buffer layer on a substrate, forming a high velocity layer on the buffer layer, forming a medium velocity layer on the high velocity layer, forming a low velocity layer on the medium velocity layer, forming a piezoelectric layer on the low velocity layer, and forming an electrode on the piezoelectric layer. Preferably, the buffer layer includes silicon oxide, the high velocity layer includes graphene, the medium velocity layer includes silicon oxynitride, and the low velocity layer includes titanium oxide.

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, an inter-metal dielectric (IMD) layer on the substrate, a MTJ in the IMD layer on the MTJ region, a first metal interconnection in the IMD layer on the logic region, and protrusions adjacent to two sides of the first metal interconnection. Preferably, the MTJ further includes a bottom electrode, a fixed layer, a barrier layer, a free layer, and a top electrode.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region, forming a fin NMOS transistor on the first NMOS region, forming a fin PMOS transistor on the first PMOS region, forming a planar NMOS transistor on the second NMOS region, forming a planar PMOS transistor on the second PMOS region, and forming a planar MOS capacitor on the MOS capacitor region.

Abstract: An electronic device includes a substrate including a first surface and a second surface opposite to the first surface; a first data line and a second data line disposed on the first surface of the substrate and extending along a first direction; a first electronic unit disposed on the first surface of the substrate; a first control unit disposed on the first surface of the substrate; a first scan line crossing the first data line and the second data line, wherein the first control unit is electrically connected between the first electronic unit and the first scan line; a first switch element disposed on the first surface of the substrate, and comprising a first gate; a first conductive pad disposed on the second surface of the substrate; and a first signal line electrically connected between the first gate of the first switch element and the first conductive pad.

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first fin-shaped structure extending along a first direction on the first region, a double diffusion break (DDB) structure extending along a second direction to divide the first fin-shaped structure into a first portion and a second portion, and a first gate structure and a second gate structure extending along the second direction on the DDB structure.

Abstract: An electronic device includes a substrate, a circuit structure, a light blocking layer and an opening. The circuit structure is disposed on the substrate and includes at least one data wire, at least one scan wire, a plurality of primary bonding pads, and a plurality of reserved bonding pads. The plurality of primary bonding pads are configured to be bonded with electronic elements, and the plurality of reserved bonding pads are configured to be bonded with repair or backup electronic elements. The light blocking layer is disposed on the substrate and overlapping with the circuit structure. A material of the light blocking layer includes metal. The opening is surrounded and enclosed by the light blocking layer, and configured to allow ambient light to penetrate. The opening does not overlap with the plurality of primary bonding pads and the plurality of reserved bonding pads.

Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a non-metal-oxide semiconductor capacitor (non-MOSCAP) region and a MOSCAP region, forming a fin-shaped structure on the MOSCAP region, forming a shallow trench isolation (STI) around the substrate and the fin-shaped structure, performing a first etching process to remove part of the STI on the MOSCAP region, and then performing a second etching process to remove part of the STI on the non-MOSCAP region and the MOSCAP region.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a non-metal-oxide semiconductor capacitor (non-MOSCAP) region and a MOSCAP region, forming a first fin-shaped structure on the MOSCAP region, performing a monolayer doping (MLD) process on the first fin-shaped structure, and then performing an anneal process for driving dopants into the first fin-shaped structure. Preferably, the MLD process is further accomplished by first performing a wet chemical doping process on the first fin-shaped structure and then forming a cap layer on the non-MOSCAP region and the MOSCAP region.

Abstract: A semiconductor device includes a bottom portion, a middle portion, a top portion, and a base portion between the bottom portion and the substrate. Preferably, the bottom portion is surrounded by a shallow trench isolation (STI), a gate oxide layer is disposed on the fin-shaped structure and the STI, a bottom surface of the gate oxide layer is higher than a top surface of the base portion, a width of a top surface of the bottom portion is greater than half the width of the bottom surface of the bottom portion, and a tip of the top portion includes a tapered portion.

Abstract: An electronic device includes a substrate and a wiring structure disposed on the substrate. The substrate includes a first surface, a second surface, a first side surface, and a second side surface. The wiring structure includes a first wiring, a second wiring, a third wiring, a first pad, and a second pad, the first pad is electrically connected to the first wiring through the second wiring, and the second pad is electrically connected to the first wiring through the third wiring. The second wiring includes a first line segment disposed on the first surface, a second line segment disposed on the first side surface, and a third line segment disposed on the second surface. The third wiring includes a fourth line segment disposed on the first surface, a fifth line segment disposed on the second side surface, and a sixth line segment disposed on the second surface.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising a non-metal-oxide semiconductor capacitor (non-MOSCAP) region and a MOSCAP region, forming a first fin-shaped structure on the MOSCAP region, forming a doped layer on the substrate of the non-MOSCAP region and the first fin-shaped structure on the MOSCAP region, removing the doped layer on the non-MOSCAP region, and then performing an anneal process to drive dopants from the doped layer into the first fin-shaped structure.

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the first fin-shaped structure into a first portion and a second portion, and more than two gate structures on the SDB structure. Preferably, the more than two gate structures include a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure disposed on the SDB structure.

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first fin-shaped structure extending along a first direction on the first region, a double diffusion break (DDB) structure extending along a second direction to divide the first fin-shaped structure into a first portion and a second portion, and a first gate structure and a second gate structure extending along the second direction on the DDB structure.

Abstract: An electronic device including a substrate, an electronic unit, a data line, a control unit, a test pad and a test switch element is provided by the present disclosure. The substrate includes a first surface and a second surface opposite to the first surface, wherein the first surface includes an active area. The electronic unit is disposed on the substrate and located in the active area. The data line is disposed on the substrate. The control unit is disposed on the substrate and located in the active area, and the control unit is electrically connected between the electronic unit and the data line. The test pad is disposed on the second surface of the substrate. The test switch element is disposed on the substrate and located in the active area, and the test switch element is electrically connected between the data line and the test pad.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a first inter-metal dielectric (IMD) layer on a substrate, forming a first trench and a second trench in the first IMD layer, forming a bottom electrode in the first trench and the second trench, forming a ferroelectric (FE) layer on the bottom electrode, and then forming a top electrode on the FE layer to form a ferroelectric random access memory (FeRAM).

Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.

Abstract: An embodiment of the disclosure provides an electronic device including multiple units. Each unit in the units includes multiple primary bonding regions and at least one reserved bonding region. Each reserved bonding region is connected to the primary bonding regions. The number of the at least one reserved bonding region is less than the number of primary bonding regions.