Patents by Inventor Chun-Hsien Lin

Chun-Hsien Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200212019
    Abstract: An electronic package is provided, including: a first substrate having a first insulating portion; a first electronic component disposed on the first substrate; a second substrate having a second insulating portion and stacked on the first substrate through a plurality of conductive elements; and a first encapsulant formed between the first substrate and the second substrate. The first insulating portion of the first substrate differs in rigidity from the second insulating portion of the second substrate. As such, during a high temperature process, one of the first substrate and the second substrate pulls at the other to bend toward the same direction, thereby reducing warpage deviation of the overall electronic package. The present invention further provides a method for fabricating the electronic package.
    Type: Application
    Filed: March 12, 2020
    Publication date: July 2, 2020
    Inventors: Chi-Rui Wu, Fu-Tang Huang, Chia-Cheng Chen, Chun-Hsien Lin, Hsuan-Hao Mi, Yu-Cheng Pai
  • Publication number: 20200211433
    Abstract: A display apparatus includes a pixel array, a plurality of gate lines and a plurality of de-load lines. The pixel array includes a plurality of display rows, each of the display rows includes a plurality of pixel circuits, and each of the pixel circuits includes a first transistor and a second transistor coupled in series between a data line and a display pixel. A control end of the first transistor of each of the pixel circuits is coupled to one of the gate lines for receiving a gate driving signal. A control end of the second transistor of each of the pixel circuits is coupled to one of the de-load lines for receiving a de-loading signal. Where an enable time period of the de-loading signal received by each of the pixel circuits covers an enable time period of the gate driving signal received by each of the pixel circuits.
    Type: Application
    Filed: June 14, 2019
    Publication date: July 2, 2020
    Applicant: Au Optronics Corporation
    Inventors: Chun-Feng Lin, Chuang-Cheng Yang, Ming-Hsien Lee, Yi-Cheng Lin, Wei-Chia Chiu
  • Patent number: 10700161
    Abstract: A manufacturing method of a substrate structure includes the following steps. A first build-up circuit structure is formed. At least one copper pillar is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer wraps the copper pillar. A second build-up circuit structure and a capacitive element are formed on the dielectric layer. In particular, the second build-up circuit structure and the first build-up circuit structure are respectively located at two opposite sides of the dielectric layer. The capacitive element is disposed in a capacitive element setting region within the second build-up circuit structure. The copper pillar penetrates the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure. A substrate structure obtained by the manufacturing method of the substrate structure is provided.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: June 30, 2020
    Assignee: Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Fu-Yang Chen, Chun-Hsien Chien, Chien-Chou Chen, Wei-Ti Lin
  • Patent number: 10699119
    Abstract: Methods and systems for detecting objects from aerial imagery are disclosed. The method includes obtaining an image of an area, obtaining a plurality of regional aerial images from the image of the area, classifying the plurality of regional aerial images as a first class or a second class by a classifier, wherein: the first class indicates a regional aerial image contains a target object, the second class indicates a regional aerial image does not contain a target object, and the classifier is trained by first and second training data, wherein the first training data include first training images containing target objects, and the second training data include second training images containing target objects obtained by adjusting at least one of brightness, contrast, color saturation, resolution, or a rotation angle of the first training images; and recognizing a target object in a regional aerial image in the first class.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: June 30, 2020
    Assignee: GEOSAT AEROSPACE & TECHNOLOGY
    Inventors: Cheng-Fang Lo, Zih-Siou Chen, Chang-Rong Ko, Chun-Yi Wu, Ya-Wen Cheng, Kuang-Yu Chen, Hsiu-Hsien Wen, Te-Che Lin, Ting-Jung Chang
  • Patent number: 10700049
    Abstract: A light-emitting diode package structure includes a carrier, at least one self-assembled material layer, a first solder mask layer, and at least one light-emitting diode. The carrier includes a first build-up circuit. The self-assembled material layer is disposed on the first build-up circuit. The first solder mask layer is disposed on the first build-up circuit. The first solder mask layer has at least one opening to expose a portion of the self-assembled material layer. The light-emitting diode is disposed on the first build-up circuit. The light-emitting diode has a self-assembled pattern. The light-emitting diode is self-assembled into the opening of the first solder mask layer through a force between the self-assembled pattern and the self-assembled material layer. A manufacturing method of the light-emitting diode package structure is also provided.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: June 30, 2020
    Assignee: Unimicron Technology Corp.
    Inventors: Wei-Ti Lin, Chun-Hsien Chien, Fu-Yang Chen
  • Patent number: 10700163
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.
    Type: Grant
    Filed: November 18, 2018
    Date of Patent: June 30, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Te-Chang Hsu, Che-Hsien Lin, Cheng-Yeh Huang, Chun-Jen Huang, Yu-Chih Su, Yao-Jhan Wang
  • Publication number: 20200196711
    Abstract: An automatic lacing mechanism automatically laces between two shoe pieces, and includes a clamping module, a positioning module, a shoelace-running module, and a shoelace-arranging module. The clamping module is adapted to fixedly clamp shoe pieces. The positioning module is adapted to position the shoe pieces prior to the shoe pieces are fixedly clamped, so that the clamping module could firmly clamp the shoe pieces. The shoelace-running module is adapted to run the shoelace through the lace eyelets on the shoe pieces. The shoelace-arranging module is adapted to change the direction of the shoelace during lacing. The positioning module has two positioning pins, wherein a distance therebetween is adjustable, and therefore the positioning module is suitable for the positioning of footwear having different distances between its lace eyelets, which could make the automatic lacing process smoother.
    Type: Application
    Filed: December 23, 2019
    Publication date: June 25, 2020
    Applicant: IDEA (MACAO COMMERCIAL OFFSHORE) LIMITED
    Inventors: CHANG-CHEN YANG, Po-Chih Lin, Chun-Hsien Ou
  • Publication number: 20200202795
    Abstract: A display device includes a driving circuit and a control circuit. The driving circuit is configured to receive a data voltage in response to a scanning signal, and to control the brightness of a light emitting element according to the data voltage. The control circuit is configured to provide a stop signal to the driving circuit in response to a digital signal and the scanning signal, so as to stop the light emitting element from emitting light, and in turn control the light emission period of the light emitting element.
    Type: Application
    Filed: December 10, 2019
    Publication date: June 25, 2020
    Inventors: Chun-Feng Lin, Kai-Wei Hong, Chuang-Cheng Yang, Yi-Cheng Lin, Ming-Hsien Lee
  • Patent number: 10690143
    Abstract: A fan blade includes a hub and a plurality of vanes. The vanes are connected to the hub. Each of the vanes includes a main body and a guide plate. The main body has an inflow surface and an outflow surface. The guide plate is disposed on the outflow surface. When the fan blade rotates, an airflow occurs and flows into a side of the fan blade via the inflow surface, and the guide plate guides part of the airflow to flow out of another side of the fan blade in a first direction and a second direction so as to cool an electronic component disposed adjacent to the another side of the fan blade.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: June 23, 2020
    Assignee: COOLER MASTER CO., LTD.
    Inventors: Tsung-Wei Lin, Chun-Hsien Chen
  • Patent number: 10693039
    Abstract: A light-emitting device comprises a light-emitting stack; a reflective structure comprising a reflective layer on the light-emitting stack and a first insulating layer covering the reflective layer; and a first conductive layer on the reflective structure; wherein the first insulating layer isolates the reflective layer from the first conductive layer.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: June 23, 2020
    Assignee: Epistar Corporation
    Inventors: Wen-Luh Liao, Shao-Ping Lu, Hung-Ta Cheng, Shih-I Chen, Chia-Liang Hsu, Shou-Chin Wei, Ching-Pei Lin, Yu-Ren Peng, Chien-Fu Huang, Wei-Yu Chen, Chun-Hsien Chang
  • Publication number: 20200194058
    Abstract: The present invention provides a static random access memory (SRAM), the SRAM includes a substrate, a SRAM pattern disposed on the substrate, wherein the SRAM pattern at least includes a first gate structure, a second gate structure and a third gate structure, arranged along a first direction, wherein the second gate structure and the third gate structure are parallel to the first gate structure, and a gap is disposed between the second gate structure and the third gate structure, and wherein the first gate structure is composed of a first elongated structure, a second elongated structure and a curved structure disposed between the first elongated structure and the second elongated structure, and wherein the curved structure is aligned with the gap along a second direction, and an interconnection contact structure disposed between the first gate structure and the second gate structure, and arranged along the first direction.
    Type: Application
    Filed: December 12, 2018
    Publication date: June 18, 2020
    Inventors: Te-Chang Hsu, Cheng-Pu Chiu, Chun-Jen Huang, Cheng-Yeh Huang, Che-Hsien Lin, Yao-Jhan Wang
  • Publication number: 20200194316
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.
    Type: Application
    Filed: February 26, 2020
    Publication date: June 18, 2020
    Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
  • Publication number: 20200196440
    Abstract: A composite substrate structure includes a circuit substrate, a first anisotropic conductive film, a first glass substrate, a dielectric layer, a patterned circuit layer and a conductive via. The first anisotropic conductive film is disposed on the circuit substrate. The first glass substrate is disposed on the first anisotropic conductive film and has a first surface and a second surface opposite to the first surface. The first glass substrate includes a first circuit layer, a second circuit layer and at least one first conductive via. The first circuit layer is disposed on the first surface. The second circuit layer is disposed on the second surface. The first conductive via penetrates the first glass substrate and is electrically connected to the first circuit layer and the second circuit layer. The first glass substrate and the circuit substrate are respectively located on two opposite sides of the first anisotropic conductive film.
    Type: Application
    Filed: February 22, 2019
    Publication date: June 18, 2020
    Applicant: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Pei-Wei Wang, Bo-Cheng Lin, Chun-Hsien Chien, Chien-Chou Chen
  • Publication number: 20200192437
    Abstract: An expansion hinge including a torque module, two first brackets, two sliding brackets, two second brackets and two elastic modules is provided. The torque module is configured to provide torques. The two first brackets are rotatably connected to two opposite ends of the torque module. The two sliding brackets are rotatably connected to the two opposite ends of the torque module. The two second brackets are slidably disposed in the two sliding brackets respectively. Each of the two elastic modules is disposed between the respective sliding bracket and the respective second bracket. The two sliding brackets are adapted to synchronously slide with respect to the two second brackets, and each of the elastic modules is configured to push the respective sliding bracket and the respective second bracket to form a pulled-out state or a pushed-in state.
    Type: Application
    Filed: November 27, 2019
    Publication date: June 18, 2020
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Che-Hsien Lin, Chun-An Shen
  • Publication number: 20200194384
    Abstract: A substrate structure includes a glass substrate, a first circuit layer, a second circuit layer, and at least one conductive region. The glass substrate has a first surface and a second surface opposing the first surface. The first circuit layer is disposed on the first surface. The second circuit layer is disposed on the second surface. The conductive region includes a plurality of conductive micro vias. The conductive micro vias penetrate through the glass substrate. The conductive micro vias are electrically connected to the first circuit layer and the second circuit layer, and the conductive micro vias have a via size of 2 ?m to 10 ?m.
    Type: Application
    Filed: November 5, 2019
    Publication date: June 18, 2020
    Applicant: Unimicron Technology Corp.
    Inventors: Chun-Hsien Chien, Po-Chen Lin, Wen-Liang Yeh, Chien-Chou Chen
  • Publication number: 20200185525
    Abstract: A semiconductor structure includes a semiconductor substrate, at least a silicon germanium (SiGe) epitaxial region disposed in the semiconductor substrate, and a contact structure disposed on the SiGe epitaxial region. The contact structure includes a titanium nitride (TiN) barrier layer and a metal layer surrounded by the TiN barrier layer. A crystalline titanium germanosilicide stressor layer is disposed in the SiGe epitaxial region and between the TiN barrier layer and the SiGe epitaxial region.
    Type: Application
    Filed: February 14, 2020
    Publication date: June 11, 2020
    Inventors: Cheng-Yeh Huang, Te-Chang Hsu, Chun-Jen Huang, Che-Hsien Lin, Yao-Jhan Wang
  • Publication number: 20200178930
    Abstract: A method and a system for evaluating a cardiac status, an electronic device and an ultrasonic scanning device are provided. The method includes: obtaining at least first image, wherein each of the first images is a two-dimensional image and includes a first cardiac image; training a depth learning model by the first image; and analyzing at least one second image by using the trained depth learning model to automatically evaluate a cardiac status of a user, wherein each of the second image is the two-dimensional image and includes a second cardiac image.
    Type: Application
    Filed: May 22, 2019
    Publication date: June 11, 2020
    Applicant: Acer Incorporated
    Inventors: Chun-Kai Huang, Ai-Hsien Li, Yen-Ju Hsiao, Yun-Ting Lin
  • Publication number: 20200184671
    Abstract: An image processing method includes the following steps: dividing an object block into a two-dimensional image; identifying at least one view hotspot in a viewing field corresponding to pupil gaze direction; receiving the view hotspot and an indicator signal; wherein the indicator signal is used to remark the object block; and generating a mask block that corresponds to the object block according to the view hotspot; wherein the indicator signal determines the label of the mask block.
    Type: Application
    Filed: October 31, 2019
    Publication date: June 11, 2020
    Applicant: HTC Corporation
    Inventors: Tung-Ting YANG, Chun-Li WANG, Cheng-Hsien LIN, Hung-Yi YANG
  • Publication number: 20200184229
    Abstract: A people-flow analysis system includes an image source, a computing device, and a host. The image source captures a first image and a second image. The computing device is connected to the image source. The computing device identifies the first image according to a data set to generate a first detecting image. The first detecting image has a position box corresponding to a pedestrian in the first image. The computing device generates a tracking image according to the data set and a difference between the first detecting image and the second image. The tracking image has another position box corresponding to a pedestrian in the second image. The host is connected to the computing device and generates a people-flow list according to the first detecting image and the tracking image.
    Type: Application
    Filed: July 8, 2019
    Publication date: June 11, 2020
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: BING-FEI WU, CHUN-HSIEN LIN, PO-WEI HUANG, MENG-LIANG CHUNG
  • Patent number: D886819
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: June 9, 2020
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Shu-Hung Lin, Wang-Hung Yeh, Hsin-Chieh Fang, Ching-Shiang Chang, Che-Hsien Lin, Che-Hsien Chu, Chun-An Shen