Abstract: An electronic device includes a substrate, an array circuit, a first distribution terminal, a second distribution terminal, a first power input terminal, a first wire and a second wire. The first distribution terminal and the second distribution terminal are disposed on a side surface of the substrate and are electrically connected to the array circuit. The first power input terminal, the first wire and the second wire are disposed on a bottom surface of the substrate. A first end of the first power input terminal is electrically connected to the first distribution terminals through the first wire. A second end of the first power input terminal opposite to the first end is electrically connected to the second distribution terminals through the second wire. A minimum distance between the first end and the first distribution terminal is less than a minimum distance between the second end and the first distribution terminal.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a fin-shaped structure on a substrate, forming a gate material layer on the fin-shaped structure, performing an etching process to pattern the gate material layer for forming a gate structure and a silicon residue, performing an ashing process on the silicon residue, and then performing a cleaning process to transform the silicon residue into a polymer stop layer on a top surface and sidewalls of the fin-shaped structure.

Abstract: A method for fabricating a static random access memory (SRAM) includes the steps of: forming a gate structure on a substrate; forming an epitaxial layer adjacent to the gate structure; forming a first interlayer dielectric (ILD) layer around the gate structure; transforming the gate structure into a metal gate; forming a contact hole exposing the epitaxial layer, forming a barrier layer in the contact hole, forming a metal layer on the barrier layer, and then planarizing the metal layer and the barrier layer to form a contact plug. Preferably, a bottom portion of the barrier layer includes a titanium rich portion and a top portion of the barrier layer includes a nitrogen rich portion.

Abstract: A repairing structure includes a signal line, a first insulation layer and a second insulation layer. The first insulation layer is disposed on the signal line. The second insulation layer is disposed on the first insulation layer. The first insulation layer includes a first hole, and the first hole overlaps a part of the signal line. The second insulation layer includes a second hole, and the first hole and the second hole at least partially overlap. Therefore, the design of the repairing structure is simple, or the repairing time may be decreased, so as to increase the convenience of use.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal-oxide semiconductor (MOS) transistor on a substrate, forming an interlayer dielectric (ILD) layer on the MOS transistor, forming a ferroelectric field effect transistor (FeFET) on the ILD layer, and forming a ferroelectric random access memory (FeRAM) on the ILD layer. The formation of the FeFET further includes first forming a semiconductor layer on the ILD layer, forming a gate structure on the semiconductor layer, and then forming a source/drain region adjacent to the gate structure.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.

Abstract: Disclosed is a display panel including a substrate, a light-emitting unit, a pixel circuit, a scan driver, and an emission driver. The light-emitting unit is arranged on the substrate. The pixel circuit is arranged on the substrate. The pixel circuit includes a data input transistor, a driving transistor, and an emission transistor. The data input transistor is configured to receive a data signal according to a scan signal. The driving transistor is configured to provide a driving current based on the data signal. The emission transistor is configured to transfer the driving current to the light-emitting unit according to an emission signal. The scan driver is arranged on the substrate and is configured to output the scan signal. The emission driver is arranged on the substrate and is configured to output the emission signal. The pixel circuit is arranged between the scan driver and the emission driver.

Abstract: A one-time programmable (OTP) memory cell includes a substrate having a first conductivity type and having an active area surrounded by an isolation region, a transistor disposed on the active area, and a capacitor disposed on the active area and electrically coupled to the transistor. The capacitor comprises a diffusion region of a second conductivity type in the substrate, a metallic film in direct contact with the active area, a capacitor dielectric layer on the metallic film, and a metal gate surrounded by the capacitor dielectric layer. The diffusion region and the metallic film constitute a capacitor bottom plate.

Abstract: A method for fabricating a surface acoustic wave (SAW) device includes the steps of forming a first dielectric layer on a substrate, forming a piezoelectric layer on the first dielectric layer, forming a second dielectric layer on the piezoelectric layer, performing a photo-etching process to remove the second dielectric layer for forming a recess in the second dielectric layer, forming a metal layer in the recess, and then performing a planarizing process to remove the metal layer for forming an electrode in the recess.

Abstract: A method for fabricating a surface acoustic wave (SAW) device includes the steps of forming a buffer layer on a substrate, forming a high velocity layer on the buffer layer, forming a medium velocity layer on the high velocity layer, forming a low velocity layer on the medium velocity layer, forming a piezoelectric layer on the low velocity layer, and forming an electrode on the piezoelectric layer. Preferably, the buffer layer includes silicon oxide, the high velocity layer includes graphene, the medium velocity layer includes silicon oxynitride, and the low velocity layer includes titanium oxide.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a fin-shaped structure on a substrate, forming a gate material layer on the fin-shaped structure, performing an etching process to pattern the gate material layer for forming a gate structure and a silicon residue, performing an ashing process on the silicon residue, and then performing a cleaning process to transform the silicon residue into a polymer stop layer on a top surface and sidewalls of the fin-shaped structure.

Abstract: The disclosure provides a display panel and a spliced display device. The display panel includes a substrate, an array circuit, and a power supply circuit. The substrate includes a top surface, a bottom surface, and a side surface located between the top surface and the bottom surface. The array circuit is disposed on the top surface. Power is supplied to the array circuit through the power supply circuit. The power supply circuit has a power input terminal. The power input terminal corresponds to at least two distribution terminals. The at least two distribution terminals are disposed on the side surface and distribute the power to different portions of the array circuit.

Abstract: A method for fabricating a static random access memory (SRAM) includes the steps of: forming a gate structure on a substrate; forming an epitaxial layer adjacent to the gate structure; forming a first interlayer dielectric (ILD) layer around the gate structure; transforming the gate structure into a metal gate; forming a contact hole exposing the epitaxial layer, forming a barrier layer in the contact hole, forming a metal layer on the barrier layer, and then planarizing the metal layer and the barrier layer to form a contact plug. Preferably, a bottom portion of the barrier layer includes a titanium rich portion and a top portion of the barrier layer includes a nitrogen rich portion.

Abstract: An electronic device is provided, which is for coupling to another electronic device in a side-by-side manner, and the electronic device includes a substrate, a first thermal dissipation sheet and a thermal dissipation element. The substrate includes a first surface and a second surface. The first thermal dissipation sheet is disposed on the first surface. The thermal dissipation element is disposed on the substrate. The first thermal dissipation sheet is disposed between the thermal dissipation element and the substrate, and the thermal dissipation element at least partially overlaps the first thermal dissipation sheet.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.

Abstract: A method for fabricating an one time programmable (OTP) device includes the steps of: forming a first gate structure and a second gate structure extending along a first direction on a substrate; forming a diffusion region adjacent to two sides of the first gate structure and the second gate structure; forming a silicide layer adjacent to the first gate structure; and patterning the first gate structure for forming a third gate structure and a fourth gate structure.

Abstract: A display device includes a first substrate, a light-emitting element, a light conversion layer, and a color filter layer. The light-emitting element is disposed on the first substrate. The light conversion layer is disposed on the light-emitting element. In addition, the color filter layer is overlapped the light-emitting element and the light conversion layer.

Abstract: An embodiment of the disclosure provides a circuit substrate and a tiled electronic device. The circuit substrate includes a substrate and first to third metal layers. The first metal layer is disposed on the substrate and includes first and second connection lines, and first and second scan lines. The first and second connection lines are electrically connected to the first and second scan lines, respectively. The second scan line includes two separate line segments respectively located at opposite sides of the first connection line. The second metal layer is disposed on the substrate and includes a first data line. The first data line is overlapped with the first connection line. The third metal layer is disposed on the substrate and includes a bridge line. The bridge line is electrically connected to the line segments. The second metal layer is disposed between the first and third metal layers.

Abstract: A manufacturing method of an electronic device is provided by the present disclosure. The method includes: providing a substrate including a non-discarding portion and a discarding portion adjacent to the non-discarding portion; forming a first test wiring extending through the non-discarding portion and the discarding portion; cutting the substrate on a target line, wherein the target line is aligned with a boundary between the non-discarding portion and the discarding portion; performing a first conducting test on the first test wiring; and determining the substrate to be in an off-target cutting state when a result of the first conducting test is a short circuit state, or determining the substrate to be in an on-target cutting state when the result of the first conducting test is an open circuit state.

Abstract: An integrated circuit layout includes a first standard cell and a second standard cell. The first standard cell includes first gate lines arranged along a first direction and extending along a second direction. The second standard cell abuts to one side of the first standard cell along the second direction and includes second gate lines arranged along the first direction and extending along the second direction. A first gate line width of the first gate lines and a second gate line width of the second gate lines are different. A first cell width of the first standard cell and a second cell width of the second standard cell are integral multiples of a default gate line pitch of the first gate lines and the second gate lines. At least some of the second gate lines and at least some of the first gate lines are aligned along the second direction.