Patents by Inventor Chun-Hsien Lin

Chun-Hsien Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10361179
    Abstract: Provided is a display device, which includes a substrate, a transistor, a capacitor and a light emitting unit. The transistor and the capacitor are disposed on the substrate. The light emitting unit is disposed on the substrate and arranged corresponding to the capacitor. The light emitting unit includes a first light emitting diode. The first light emitting diode is electrically connected with the transistor and overlaps the capacitor. The display device has favorable space utilization, provides a repair function, or reduces the probability of failure.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: July 23, 2019
    Assignee: Innolux Corporation
    Inventors: Chun-Hsien Lin, Shun-Yuan Hu, Tsau-Hua Hsieh, Li-Wei Mao, Tung-Kai Liu, Shu-Ming Kuo, Chih-Yung Hsieh
  • Patent number: 10332887
    Abstract: A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a first doped region in a substrate; removing part of the first doped region to form a trench in the substrate; forming a gate structure in the trench; and forming a barrier structure between the gate structure and the first doped region.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: June 25, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Chun-Hsien Lin, Fu-Che Lee
  • Patent number: 10312238
    Abstract: A manufacturing method of a magnetic random access memory (MRAM) cell includes the following steps. A magnetic tunnel junction (MTJ) film stack is formed on an insulation layer. An aluminum mask layer is formed on the MTJ film stack. A hard mask layer is formed on the aluminum mask layer. An ion beam etching (IBE) process is performed with the aluminum mask layer and the hard mask layer as a mask. The MTJ film stack is patterned to be a patterned MTJ film stack by the IBE process, and at least apart of the aluminum mask layer is bombarded by the IBE process for forming an aluminum film on a sidewall of the patterned MTJ film stack. An oxidation treatment is performed, and the aluminum film is oxidized to be an aluminum oxide protection layer on the sidewall of the patterned MTJ film stack by the oxidation treatment.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: June 4, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsiao-Pang Chou, Yu-Ru Yang, Chih-Chien Liu, Chao-Ching Hsieh, Chun-Hsien Lin
  • Publication number: 20190164941
    Abstract: An electronic package is provided, including: a first substrate having a first insulating portion; a first electronic component disposed on the first substrate; a second substrate having a second insulating portion and stacked on the first substrate through a plurality of conductive elements; and a first encapsulant formed between the first substrate and the second substrate. The first insulating portion of the first substrate differs in rigidity from the second insulating portion of the second substrate. As such, during a high temperature process, one of the first substrate and the second substrate pulls at the other to bend toward the same direction, thereby reducing warpage deviation of the overall electronic package. The present invention further provides a method for fabricating the electronic package.
    Type: Application
    Filed: March 28, 2018
    Publication date: May 30, 2019
    Inventors: Chi-Rui Wu, Fu-Tang Huang, Chia-Cheng Chen, Chun-Hsien Lin, Hsuan-Hao Mi, Yu-Cheng Pai
  • Publication number: 20190164854
    Abstract: A display device includes a substrate, a light-emitting element, and a transistor. The substrate has a top surface. The light-emitting element is disposed on the substrate. The transistor is disposed on the substrate, and includes a drain electrode, a gate electrode, and a semiconductor layer. The drain electrode is electrically connected to the light-emitting element. The semiconductor layer includes an overlapping portion overlapped with the gate electrode. The light-emitting element does not overlap with the overlapping portion along a direction perpendicular to the top surface of the substrate.
    Type: Application
    Filed: January 10, 2019
    Publication date: May 30, 2019
    Inventors: Tung-Kai LIU, Tsau-Hua HSIEH, Wei-Cheng CHU, Chun-Hsien LIN, Chandra LIUS, Ting-Kai HUNG, Kuan-Feng LEE, Ming-Chang LIN, Tzu-Min YAN, Hui-Chieh WANG
  • Publication number: 20190157274
    Abstract: A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a first doped region in a substrate; removing part of the first doped region to form a trench in the substrate; forming a gate structure in the trench; and forming a barrier structure between the gate structure and the first doped region.
    Type: Application
    Filed: December 13, 2017
    Publication date: May 23, 2019
    Inventors: Feng-Yi Chang, Chun-Hsien Lin, Fu-Che Lee
  • Publication number: 20190147794
    Abstract: The disclosure provides a display apparatus. The display apparatus of the disclosure includes a substrate having a plurality of pixel regions, a plurality of active elements, a plurality of first signal lines and second signal lines, a plurality of ground signal lines and a plurality of light emitting diodes (LEDs). The plurality of ground signal lines are disposed on the substrate and arranged to alternate with the first signal lines. At least one LED has first and second electrodes. The first electrode of at least one LED is electrically connected with a corresponding active element. A second electrode of at least one LED is electrically connected with a corresponding ground signal line. At least two LEDs disposed in an identical pixel region is electrically connected with an identical ground signal line between two first signal lines adjacent to each other. The display apparatus of the disclosure has high resolution.
    Type: Application
    Filed: January 17, 2019
    Publication date: May 16, 2019
    Applicant: Innolux Corporation
    Inventors: Chun-Hsien Lin, Chih-Yung Hsieh, Tsau-Hua Hsieh, Shu-Ming Kuo
  • Publication number: 20190139959
    Abstract: A manufacturing method of a magnetic random access memory (MRAM) cell includes the following steps. A magnetic tunnel junction (MTJ) film stack is formed on an insulation layer. An aluminum mask layer is formed on the MTJ film stack. A hard mask layer is formed on the aluminum mask layer. An ion beam etching (IBE) process is performed with the aluminum mask layer and the hard mask layer as a mask. The MTJ film stack is patterned to be a patterned MTJ film stack by the IBE process, and at least apart of the aluminum mask layer is bombarded by the IBE process for forming an aluminum film on a sidewall of the patterned MTJ film stack. An oxidation treatment is performed, and the aluminum film is oxidized to be an aluminum oxide protection layer on the sidewall of the patterned MTJ film stack by the oxidation treatment.
    Type: Application
    Filed: November 6, 2017
    Publication date: May 9, 2019
    Inventors: Hsiao-Pang Chou, Yu-Ru Yang, Chih-Chien Liu, Chao-Ching Hsieh, Chun-Hsien Lin
  • Patent number: 10283209
    Abstract: A method for detecting problem cells of a SATA SSD and a SATA SSD having self-detecting function looking for problem cells are disclosed. The method includes the steps of: providing a detecting program used to detect aged and died cells in a SATA SSD; writing the detecting program to a MCU (Micro Control Unit) in the SATA SSD; pulling high electric potential of a communicating pin of a SATA connector of the SATA SSD to initiate the detecting program; collecting location data of aged and died cells in the SATA SSD by the detecting program; and storing the location data in a storage area in the SSD. The present invention utilizes the DAS/DSS pin as a channel to initiate detecting program. It has advantages of using current interface of SSD, no effort on taking apart hardware and automatically running the detecting program without human control.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: May 7, 2019
    Assignee: Storart Technology (Shenzhen) Co. Ltd
    Inventor: Chun Hsien Lin
  • Patent number: 10283412
    Abstract: A method for fabricating a semiconductor device is provided. A substrate having a dummy gate thereon is prepared. A spacer is disposed on a sidewall of the dummy gate. A source/drain region is disposed adjacent to the dummy gate. A sacrificial layer is then formed on the source/drain region. A cap layer is then formed on the sacrificial layer. A top surface of the cap layer is coplanar with a top surface of the dummy gate. A replacement metal gate (RMG) process is performed to transform the dummy gate into a replacement metal gate. An opening is then formed in the cap layer to expose a top surface of the sacrificial layer. The sacrificial layer is removed through the opening, thereby forming a lower contact hole exposing a top surface of the source/drain region. A lower contact plug is then formed in the lower contact hole.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: May 7, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia Chang Hsu, Chun-Hsien Lin
  • Patent number: 10276493
    Abstract: A semiconductor structure includes a conductive feature on a substrate. A plurality of first dielectric layers are disposed on the conductive feature, and stress directions of at least two of the first dielectric layers are different from one another. A first hole penetrates through the plurality of the first dielectric layers to expose the conductive feature. A first conductive plug conformally covers the first hole and is electrically connected to the conductive feature. A first insulating plug on the first conductive plug fills the first hole.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: April 30, 2019
    Assignee: VANGUARD ENTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Wei-Lun Hsia, Chun-Hsien Lin, Hsiao-Ying Yang
  • Publication number: 20190114961
    Abstract: A semiconductor device includes a first display unit and a second display unit. The first display unit includes a first substrate, first light-emitting units, and a first gate driver circuit. The first substrate includes a first display region. The first substrate has a first side and a second side. The first light-emitting units are disposed in the first display region. The first gate driver circuit is disposed in the first display region. The second display unit is adjacent to the first display unit. The second display unit includes a second substrate. The second substrate includes a second display region, second light-emitting units, and a second gate driver circuit. The second substrate has a third side and a fourth side. The second light-emitting units are disposed in the second display region. A second gate driver circuit is disposed in the second display region.
    Type: Application
    Filed: September 14, 2018
    Publication date: April 18, 2019
    Inventors: Geng-Fu CHANG, Jui-Feng KO, Tsau-Hua HSIEH, Chun-Hsien LIN, Jian-Jung SHIH
  • Publication number: 20190115508
    Abstract: A display device is provided. The display device includes a plurality of pixels. At least one of the pixels includes a semiconductor device having a light-emitting area, a first light conversion layer disposed on the semiconductor device and a first scattering layer disposed on the semiconductor device. The first scattering layer is disposed on the first light conversion layer.
    Type: Application
    Filed: September 12, 2018
    Publication date: April 18, 2019
    Inventors: Chun-Hsien LIN, Geng-Fu CHANG, Jui-Feng KO, Tsau-Hua HSIEH, Shu-Ming KUO
  • Publication number: 20190067433
    Abstract: A method for forming a tunneling field effect transistor is disclosed, which includes the following steps. First, a semiconductor substrate is provided. A source region is formed on the semiconductor substrate. A tunneling region having a sidewall and a top surface is formed on the source region. A drain region is formed on the tunneling region. A gate dielectric layer is then formed, covering the sidewall and the top surface of the tunneling region. A first metal layer is formed, covering the gate dielectric layer. Subsequently, an anisotropic etching process is performed to remove a portion of the first metal layer. After the anisotropic etching process, a second metal layer is fabricated to cover the remaining first metal layer and the gate dielectric layer.
    Type: Application
    Filed: October 28, 2018
    Publication date: February 28, 2019
    Inventors: An-Chi Liu, Chun-Hsien Lin
  • Patent number: 10217678
    Abstract: A display device includes a substrate, a first transistor, a second transistor and a conductive connection portion disposed on the substrate. The first transistor is electrically connected to the gate electrode of the second transistor through the conductive connection portion. An insulating layer is disposed on the conductive connection portion. A pixel electrode is disposed on the insulating layer and is electrically connected to the second transistor. The pixel electrode is at least partially overlapped with the conductive connection portion. A light-emitting element is disposed on the pixel electrode. The conductive connection portion and the pixel electrode form a capacitor. The capacitor has an equivalent permittivity and a thickness. The ratio of the equivalent permittivity to the thickness is in a range from 0.4*(1E+5)F/m^2 to 296.48*(1E+5)F/m^2.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: February 26, 2019
    Assignee: INNOLUX CORPORATION
    Inventors: Tung-Kai Liu, Tsau-Hua Hsieh, Wei-Cheng Chu, Chun-Hsien Lin, Chandra Lius, Ting-Kai Hung, Kuan-Feng Lee, Ming-Chang Lin, Tzu-Min Yan, Hui-Chieh Wang
  • Patent number: 10217403
    Abstract: The disclosure provides a display apparatus. The display apparatus of the disclosure includes a substrate having a plurality of pixel regions, a plurality of active elements, a plurality of first signal lines and second signal lines, a plurality of ground signal lines and a plurality of light emitting diodes (LEDs). The plurality of ground signal lines are disposed on the substrate and arranged to alternate with the first signal lines. At least one LED has first and second electrodes. The first electrode of at least one LED is electrically connected with a corresponding active element. A second electrode of at least one LED is electrically connected with a corresponding ground signal line. At least two LEDs disposed in an identical pixel region is electrically connected with an identical ground signal line between two first signal lines adjacent to each other. The display apparatus of the disclosure has high resolution.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: February 26, 2019
    Assignee: Innolux Corporation
    Inventors: Chun-Hsien Lin, Chih-Yung Hsieh, Tsau-Hua Hsieh, Shu-Ming Kuo
  • Publication number: 20190043801
    Abstract: A semiconductor structure includes a conductive feature on a substrate. A plurality of first dielectric layers are disposed on the conductive feature, and stress directions of at least two of the first dielectric layers are different from one another. A first hole penetrates through the plurality of the first dielectric layers to expose the conductive feature. A first conductive plug conformally covers the first hole and is electrically connected to the conductive feature. A first insulating plug on the first conductive plug fills the first hole.
    Type: Application
    Filed: August 1, 2017
    Publication date: February 7, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Wei-Lun HSIA, Chun-Hsien LIN, Hsiao-Ying YANG
  • Publication number: 20190044023
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of light-emitting elements on a first substrate and forming a first pattern array on a second substrate. The method also includes transferring the plurality of light-emitting elements from the first substrate to the second substrate. The method further includes forming the first pattern array on a third substrate. In addition, the method includes transferring the plurality of light-emitting elements from the second substrate to the third substrate. The method also includes forming a second pattern array on a fourth substrate. The method further includes transferring the plurality of light-emitting elements from the third substrate to the fourth substrate. The pitch between the plurality of light-emitting elements on the first substrate is different than the pitch of the first pattern array.
    Type: Application
    Filed: June 7, 2018
    Publication date: February 7, 2019
    Inventors: Kai CHENG, Tsau-Hua HSIEH, Fang-Ying LIN, Tung-Kai LIU, Hui-Chieh WANG, Chun-Hsien LIN, Jui-Feng KO
  • Publication number: 20190043979
    Abstract: A method for fabricating a tunnel field effect transistor (TFET) includes the steps of providing a substrate and then forming an interfacial layer on the substrate. Preferably, the step of forming the interfacial layer includes the steps of: performing a plasma treatment process to inject a first gas containing nitrogen; injecting a second gas containing oxygen; and injecting a precursor to react with the first gas and the second gas for forming the interfacial layer.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 7, 2019
    Inventors: An-Chi Liu, Chun-Hsien Lin
  • Patent number: 10199277
    Abstract: A semiconductor structure includes a stacked metal oxide layer on a substrate, wherein the stacked metal oxide layer includes a first metal oxide layer, a second metal oxide layer, and a third metal oxide layer from top to bottom, and the energy bandgap of the second metal oxide layer is lower than the energy bandgap of the first metal oxide layer and that of the third metal oxide layer. The semiconductor structure includes a metal oxide layer on a substrate, wherein the energy bandgap of the metal oxide layer changes along a direction perpendicular to the surface of the substrate. The present invention also provides a semiconductor process forming said semiconductor structure.
    Type: Grant
    Filed: September 18, 2016
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chen-Kuo Chiang, Chun-Hsien Lin