Patents by Inventor Chun-Hsien Lin

Chun-Hsien Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200381615
    Abstract: A semiconductor device includes: a substrate having a magnetic tunneling junction (MTJ) region and a logic region; an inter-metal dielectric (IMD) layer on the substrate; a first metal interconnection in the IMD layer on the logic region; and protrusions adjacent to two sides of the first metal interconnection. Preferably, the first metal interconnection further includes a via conductor and a trench conductor and the protrusions includes a first protrusion on one side of the via conductor and a second protrusion on another side of the via conductor.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 3, 2020
    Inventors: An-Chi Liu, Chun-Hsien Lin
  • Patent number: 10854520
    Abstract: The present invention provides a method for forming a semiconductor structure. The method including: Firstly, a substrate is provided, a first region and a second region are defined thereon, next, a gate dielectric layer and a work function metal layer are sequentially formed on the substrate within the first region and within the second region. Afterwards, a dielectric layer is formed on the work function metal layer within the second region, a hydrogen gas treatment is then performed on the substrate, and the work function metal layer is removed within the first region.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: December 1, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Chun-Hsien Lin, Wei-Hao Huang, Kai-Teng Cheng
  • Patent number: 10854613
    Abstract: A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a first doped region in a substrate; removing part of the first doped region to form a trench in the substrate; forming a gate structure in the trench; and forming a barrier structure between the gate structure and the first doped region.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: December 1, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Chun-Hsien Lin, Fu-Che Lee
  • Publication number: 20200363513
    Abstract: Disclosures of the present invention describe an optical proximity sensor, which is particularly designed to have functionality of canceling an ambient light noise and/or an optical crosstalk noise by using light-to-frequency conversion technique, and comprises: a controlling and processing circuit, a lighting unit, a light receiving unit, an analog adder, a first DAC unit, a second DAC unit, and a light-to-digital conversion (LDC) unit. In the controlling of the controlling and processing circuit, the first DAC unit and the second DAC unit would respectively generate a first compensation current signal and a second compensation current signal to the analog adder, such that a noise signal of ambient light and a noise signal of optical crosstalk existing in an optical current signal of object reflection light would be canceled by the two compensation current signals in the analog adder.
    Type: Application
    Filed: June 23, 2019
    Publication date: November 19, 2020
    Inventors: WEN-SHENG LIN, SHENG-CHENG LEE, YU-CHENG SU, PENG-HAN CHAN, CHUN-HSIEN LIN
  • Publication number: 20200348772
    Abstract: A touch display device is provided in this disclosure. The touch display device includes a substrate, a first conductive layer, a second conductive layer, a stacked structure, an inorganic light emitting unit, and a touch sensing circuit. The first conductive layer is disposed on the substrate. The first conductive layer includes a gate electrode. The second conductive layer is disposed on the first conductive layer. The second conductive layer includes a source electrode and a drain electrode. The stacked structure is disposed on the substrate. The staked structure includes a conductive channel and a sensing electrode. The inorganic light emitting unit is disposed on the stacked structure. The inorganic light emitting unit is electrically connected with the drain electrode via the conductive channel. The touch sensing circuit is electrically connected with the sensing electrode.
    Type: Application
    Filed: April 6, 2020
    Publication date: November 5, 2020
    Inventors: Po-Yang Chen, Hsing-Yuan Hsu, Tzu-Min Yan, Chun-Hsien Lin, Kuei-Sheng Chang
  • Publication number: 20200333754
    Abstract: A light sensor device is provided. It is controlled with a dual-mode master-and-slave microcontroller unit (MCU) application. An MCU is embedded into a light sensor chip. The original dual-mode master-and-slave dual-CPU architectures are combined to be operated as a single-CPU architecture. Since the original circuit pin design is followed, it is possible to be compatible with the old circuit design. The present invention uses a single-CPU architecture to directly control light sensors. Through the configuration of RAM, an inter-integrated circuit bus (I2C I/F) can be redirected to an internal non-volatile memory to switch the operational mode of the light sensor chip from a slave machine to a host machine which switches off the interrupt pin and, then, turns to a GPIO pin. Thus, the present invention provides a simple single-CPU architecture with easy use and effectively-lowered cost.
    Type: Application
    Filed: April 17, 2019
    Publication date: October 22, 2020
    Inventors: Chun-Hsien Lin, Peng-Han Chan, Wen-Sheng Lin, Yu-Cheng Su, Sheng-Cheng Lee
  • Patent number: 10803654
    Abstract: The invention is related to a method of three-dimensional face reconstruction by inputting a single face image to reconstruct a three-dimensional face model, therefore, the human face image is seen at various angles of three-dimensional face through rotating the model images.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: October 13, 2020
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Bing-Fei Wu, Chun-Hsien Lin, Yi-Chiao Wu, Bing-Jhang Wu, Chih-Cheng Huang, Meng-Liang Chung
  • Patent number: 10779739
    Abstract: The present invention provides a contactless-type sport training monitor method, comprising: selecting at least an image database to recognize a plurality of expressions in the image database; making pre-processing for the plurality of expressions: using a convolutional neural network as a feature point extraction model; acquiring a human image; tracking a first target region and a second target region in the human image; making chrominance-based rPPG trace extraction; using the deep level model to compare the second target region image; and to calculate a post-exercise heart rate recovery achievement ratio, to judge the Rating of Perceived Exertion, and judging whether the human body is under overtraining status or not.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: September 22, 2020
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Bing-Fei Wu, Chun-Hsien Lin, Po-Wei Huang, Tzu-Min Lin, Meng-Liang Chung
  • Patent number: 10776614
    Abstract: A facial expression recognition training system includes a training module, feature database, a capturing module, a recognition module and an adjusting module. The training module trains a facial expression feature capturing model according to known face images. The feature database stores known facial expression features of the known face images. The capturing module continuously captures first face images, and the facial expression feature capturing model outputs facial expression features of the first face images according to the first face images. The recognition module compares the facial expression features and the known facial expression features, and fit the facial expression features to the first known facial expression features that is one kind of the known facial expression feature accordingly. The adjusting module adjusts the facial expression feature capturing model to reduce the differences between the facial expression features and the known facial expression features.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: September 15, 2020
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Bing-Fei Wu, Chun-Hsien Lin, Meng-Liang Chung
  • Publication number: 20200285271
    Abstract: A tiled display device includes a first panel. The first panel includes a first lower substrate and a first upper substrate disposed opposite to the first lower substrate. The first upper substrate includes a first upper surface, a first lower surface and a first side surface located between the first upper surface and the first lower surface. The tiled display device further includes a second panel disposed adjacent to the first panel. The second panel includes a second lower substrate and a second upper substrate disposed opposite to the second lower substrate. The second upper substrate includes a second upper surface, a second lower surface and a second side surface located between the second upper surface and the second lower surface. The second side surface is disposed adjacent to the first side surface.
    Type: Application
    Filed: February 18, 2020
    Publication date: September 10, 2020
    Inventors: Wan-Ling Huang, Shu-Ming Kuo, Tsau-Hua Hsieh, Chun-Hsien Lin, Tzu-Min Yan
  • Publication number: 20200259044
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of light-emitting elements on a first substrate and forming a first pattern array on a second substrate. The method also includes transferring the plurality of light-emitting elements from the first substrate to the second substrate. The method further includes forming the first pattern array on a third substrate. In addition, the method includes transferring the plurality of light-emitting elements from the second substrate to the third substrate. The method also includes forming a second pattern array on a fourth substrate. The method further includes transferring the plurality of light-emitting elements from the third substrate to the fourth substrate. The pitch between the plurality of light-emitting elements on the first substrate is different than the pitch of the first pattern array.
    Type: Application
    Filed: April 27, 2020
    Publication date: August 13, 2020
    Inventors: Kai CHENG, Tsau-Hua HSIEH, Fang-Ying LIN, Tung-Kai LIU, Hui-Chieh WANG, Chun-Hsien LIN, Jui-Feng KO
  • Publication number: 20200212019
    Abstract: An electronic package is provided, including: a first substrate having a first insulating portion; a first electronic component disposed on the first substrate; a second substrate having a second insulating portion and stacked on the first substrate through a plurality of conductive elements; and a first encapsulant formed between the first substrate and the second substrate. The first insulating portion of the first substrate differs in rigidity from the second insulating portion of the second substrate. As such, during a high temperature process, one of the first substrate and the second substrate pulls at the other to bend toward the same direction, thereby reducing warpage deviation of the overall electronic package. The present invention further provides a method for fabricating the electronic package.
    Type: Application
    Filed: March 12, 2020
    Publication date: July 2, 2020
    Inventors: Chi-Rui Wu, Fu-Tang Huang, Chia-Cheng Chen, Chun-Hsien Lin, Hsuan-Hao Mi, Yu-Cheng Pai
  • Publication number: 20200194316
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.
    Type: Application
    Filed: February 26, 2020
    Publication date: June 18, 2020
    Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
  • Publication number: 20200184229
    Abstract: A people-flow analysis system includes an image source, a computing device, and a host. The image source captures a first image and a second image. The computing device is connected to the image source. The computing device identifies the first image according to a data set to generate a first detecting image. The first detecting image has a position box corresponding to a pedestrian in the first image. The computing device generates a tracking image according to the data set and a difference between the first detecting image and the second image. The tracking image has another position box corresponding to a pedestrian in the second image. The host is connected to the computing device and generates a people-flow list according to the first detecting image and the tracking image.
    Type: Application
    Filed: July 8, 2019
    Publication date: June 11, 2020
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: BING-FEI WU, CHUN-HSIEN LIN, PO-WEI HUANG, MENG-LIANG CHUNG
  • Publication number: 20200167990
    Abstract: The invention is related to a method of three-dimensional face reconstruction by inputting a single face image to reconstruct a three-dimensional face model, therefore, the human face image is seen at various angles of three-dimensional face through rotating the model images.
    Type: Application
    Filed: September 23, 2019
    Publication date: May 28, 2020
    Inventors: BING-FEI WU, CHUN-HSIEN LIN, YI-CHIAO WU, BING-JHANG WU, CHIH-CHENG HUANG, MENG-LIANG CHUNG
  • Patent number: 10658458
    Abstract: A method of forming a semiconductor structure is disclosed. A fin structure is formed on a substrate and a trench is formed in the fin structure. The trench has a top corner, an upper portion having an upper sidewall and a lower portion having a lower sidewall. A first dielectric layer is then formed on the substrate and fills the lower portion of the trench. After that, a second dielectric layer is formed on the substrate and covers the top corner and the upper sidewall of the trench. The second dielectric layer also covers an upper surface of the first dielectric layer.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: May 19, 2020
    Assignee: UNITED MICROELECTRONCIS CORP.
    Inventors: I-Ming Tseng, Chun-Hsien Lin, Wen-An Liang
  • Patent number: 10650731
    Abstract: The disclosure provides a display apparatus. The display apparatus of the disclosure includes a substrate having a plurality of pixel regions, a plurality of active elements, a plurality of first signal lines and second signal lines, a plurality of ground signal lines and a plurality of light emitting diodes (LEDs). The plurality of ground signal lines are disposed on the substrate and arranged to alternate with the first signal lines. At least one LED has first and second electrodes. The first electrode of at least one LED is electrically connected with a corresponding active element. A second electrode of at least one LED is electrically connected with a corresponding ground signal line. At least two LEDs disposed in an identical pixel region is electrically connected with an identical ground signal line between two first signal lines adjacent to each other. The display apparatus of the disclosure has high resolution.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: May 12, 2020
    Assignee: Innolux Corporation
    Inventors: Chun-Hsien Lin, Chih-Yung Hsieh, Tsau-Hua Hsieh, Shu-Ming Kuo
  • Patent number: 10651352
    Abstract: A display device is provided. The display device includes a plurality of pixels. At least one of the pixels includes a semiconductor device having a light-emitting area, a first light conversion layer disposed on the semiconductor device and a first scattering layer disposed on the semiconductor device. The first scattering layer is disposed on the first light conversion layer.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: May 12, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Chun-Hsien Lin, Geng-Fu Chang, Jui-Feng Ko, Tsau-Hua Hsieh, Shu-Ming Kuo
  • Publication number: 20200135899
    Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.
    Type: Application
    Filed: December 4, 2018
    Publication date: April 30, 2020
    Inventors: Po-Chang Lin, Bo-Han Huang, Chih-Chung Chen, Chun-Hsien Lin, Shih-Hung Tsai, Po-Kuang Hsieh
  • Patent number: 10636794
    Abstract: A magnetic tunnel junction (MTJ) structure of a magnetic random access memory (MRAM) cell includes an insulation layer, a patterned MTJ film stack, an aluminum oxide protection layer, an interlayer dielectric, and a connection structure. The patterned MTJ film stack is disposed on the insulation layer. The aluminum oxide protection layer is disposed on a sidewall of the patterned MTJ film stack, and the aluminum oxide protection layer includes an aluminum film oxidized by an oxidation treatment. The interlayer dielectric covers the aluminum oxide protection layer and the patterned MTJ film stack. The connection structure penetrates the interlayer dielectric above the patterned MTJ film stack, and the connection structure is electrically connected to a topmost portion of the patterned MTJ film stack.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: April 28, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsiao-Pang Chou, Yu-Ru Yang, Chih-Chien Liu, Chao-Ching Hsieh, Chun-Hsien Lin