Abstract: The invention provides a semiconductor structure, which comprises a first standard cell and a second standard cell located on a substrate, wherein an isolation region is included between the first standard cell and the second standard cell, a plurality of fin structures and a plurality of gates form a plurality of transistors, which are respectively located in the first standard cell and the second standard cell, and a plurality of single diffusion breaks (SDBs) located in the first standard cell and the second standard cell. A plurality of first dummy grooves in the first standard cell and the second standard cell, and a plurality of second dummy grooves in the isolation region, wherein some of the second dummy grooves overlap the first dummy grooves.

Abstract: An integrated circuit layout includes a first standard cell and a second standard cell. The first standard cell includes first gate lines arranged along a first direction and extending along a second direction. The second standard cell abuts to one side of the first standard cell along the second direction and includes second gate lines arranged along the first direction and extending along the second direction. A first gate line width of the first gate lines and a second gate line width of the second gate lines are different. A first cell width of the first standard cell and a second cell width of the second standard cell are integral multiples of a default gate line pitch of the first gate lines and the second gate lines. At least some of the second gate lines and at least some of the first gate lines are aligned along the second direction.

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first fin-shaped structure extending along a first direction on the first region, a double diffusion break (DDB) structure extending along a second direction to divide the first fin-shaped structure into a first portion and a second portion, and a first gate structure and a second gate structure extending along the second direction on the DDB structure.

Abstract: The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a first interconnect layer and a second interconnect layer. The first interconnect layer is disposed on the substrate, and the first interconnect layer includes a first dielectric layer around a plurality of first magnetic tunneling junction (MTJ) structures. The second interconnect layer is disposed on the first interconnect layer, and the second interconnect layer includes a second dielectric layer around a plurality of second MTJ structures, wherein, the second MTJ structures and the first MTJ structures are alternately arranged along a direction. The semiconductor device may obtain a reduced size of each bit cell under a permissible process window, so as to improve the integration of components.

Abstract: An electronic device includes a substrate, an array circuit, a first distribution terminal, a second distribution terminal, a first power input terminal, a first wire and a second wire. The first distribution terminal and the second distribution terminal are disposed on a side surface of the substrate and are electrically connected to the array circuit. The first power input terminal, the first wire and the second wire are disposed on a bottom surface of the substrate. A first end of the first power input terminal is electrically connected to the first distribution terminals through the first wire. A second end of the first power input terminal opposite to the first end is electrically connected to the second distribution terminals through the second wire. A minimum distance between the first end and the first distribution terminal is less than a minimum distance between the second end and the first distribution terminal.

Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a gate electrode on the barrier layer, a field plate adjacent to two sides of the gate electrode, and a first passivation layer adjacent to two sides of the gate electrode. Preferably, a sidewall of the field plate includes a first curve.

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the first fin-shaped structure into a first portion and a second portion, and more than two gate structures on the SDB structure. Preferably, the more than two gate structures include a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure disposed on the SDB structure.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a resistor region, forming a first gate structure on the resistor region, forming a first interlayer dielectric (ILD) layer around the first gate structure, transforming the first gate structure into a first metal gate having a gate electrode on the substrate and a hard mask on the gate electrode, and then forming a resistor on the first metal gate.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having an one time programmable (OTP) device region, forming a shallow trench isolation (STI) in the substrate, forming a first doped region adjacent to the STI, removing part of the STI, and then forming a first gate structure on the substrate and the STI. Preferably, the first gate structure includes a high-k dielectric layer on the substrate and a gate electrode on the high-k dielectric layer, in which the high-k dielectric layer comprises a first L-shape.

Abstract: The present disclosure provides, the semiconductor device includes a substrate, a first transistor, a capacitor, and two first plugs. The substrate has a high-voltage region and a capacitor region. The first transistor is disposed in the high-voltage region, and includes a first gate dielectric layer, a first gate electrode, and a first capping layer. The capacitor is disposed in the capacitor region and includes a second gate electrode, a second capping layer, a dielectric layer, and a conductive layer. The two first plugs are disposed on the capacitor, wherein one of the two first plugs penetrates through the second capping layer to directly contact the second gate electrode, and another one of the two first plugs directly contacts the conductive layer.

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, an inter-metal dielectric (IMD) layer on the substrate, a MTJ in the IMD layer on the MTJ region, a first metal interconnection in the IMD layer on the logic region, and protrusions adjacent to two sides of the first metal interconnection. Preferably, the MTJ further includes a bottom electrode, a fixed layer, a barrier layer, a free layer, and a top electrode.

Abstract: An electronic device and method of fabricating the same are provided herein. The electronic device includes a first main pad; a second main pad; a first repair line electrically connected to the first main pad; a second repair line electrically connected to the second main pad, wherein the first repair line and the second repair line forms a first weldable region; a first spare pad; a second spare pad; a connection line electrically connected to the second repair line, the first spare pad and the second spare pad; and a first electronic unit disposed on the first main pad and the second main pad.

Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first fin-shaped structure extending along a first direction on the first region, a double diffusion break (DDB) structure extending along a second direction to divide the first fin-shaped structure into a first portion and a second portion, and a first gate structure and a second gate structure extending along the second direction on the DDB structure.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.

Abstract: A method for expanding in a balanced manner storage capacity in a cloud without disruption of services provided by the cloud to users includes setting a capacity expansion target of a storage pool of memory devices according to disk space occupation of service currently provided by the storage system when an additional storage node is added to the storage pool of the storage system, expanding the capacity of the storage pool according to the capacity expansion target and adjusting capacity expansion parameter of the storage pool in different periods of time. An electronic device and a non-volatile storage medium performing the above-described method are also disclosed.

Abstract: A contactless physiological measurement device is disclosed. The contactless physiological measurement device is an electronic device comprising a processor and a memory storing an application program. When the application program is executed, the processor controls a front camera and a rear camera of the electronic device to photograph a user, so as to obtain a face image and a hand image. Subsequently, after extracting a first rPPG signal and a second rPPG signal from the face image and the hand image respectively, physiological parameters are calculated by apply a signal process to the first/second rPPG signal. Moreover, a signal parameter difference is also acquired after applying a signal difference calculation to the two rPPG signals. Consequently, an estimation value of blood pressure is outputted by inputting user anthropometric parameter, said signal parameter difference and at least one physiological parameter into a pre-trained blood pressure estimating model.

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a gate electrode on the barrier layer, a field plate adjacent to two sides of the gate electrode, and a first passivation layer adjacent to two sides of the gate electrode. Preferably, a sidewall of the field plate includes a first curve.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region, forming a fin NMOS transistor on the first NMOS region, forming a fin PMOS transistor on the first PMOS region, forming a planar NMOS transistor on the second NMOS region, forming a planar PMOS transistor on the second PMOS region, and forming a planar MOS capacitor on the MOS capacitor region.