Patents by Inventor Chun-Hsien Lin

Chun-Hsien Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200135899
    Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.
    Type: Application
    Filed: December 4, 2018
    Publication date: April 30, 2020
    Inventors: Po-Chang Lin, Bo-Han Huang, Chih-Chung Chen, Chun-Hsien Lin, Shih-Hung Tsai, Po-Kuang Hsieh
  • Patent number: 10636794
    Abstract: A magnetic tunnel junction (MTJ) structure of a magnetic random access memory (MRAM) cell includes an insulation layer, a patterned MTJ film stack, an aluminum oxide protection layer, an interlayer dielectric, and a connection structure. The patterned MTJ film stack is disposed on the insulation layer. The aluminum oxide protection layer is disposed on a sidewall of the patterned MTJ film stack, and the aluminum oxide protection layer includes an aluminum film oxidized by an oxidation treatment. The interlayer dielectric covers the aluminum oxide protection layer and the patterned MTJ film stack. The connection structure penetrates the interlayer dielectric above the patterned MTJ film stack, and the connection structure is electrically connected to a topmost portion of the patterned MTJ film stack.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: April 28, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsiao-Pang Chou, Yu-Ru Yang, Chih-Chien Liu, Chao-Ching Hsieh, Chun-Hsien Lin
  • Patent number: 10629572
    Abstract: An electronic package is provided, including: a first substrate having a first insulating portion; a first electronic component disposed on the first substrate; a second substrate having a second insulating portion and stacked on the first substrate through a plurality of conductive elements; and a first encapsulant formed between the first substrate and the second substrate. The first insulating portion of the first substrate differs in rigidity from the second insulating portion of the second substrate. As such, during a high temperature process, one of the first substrate and the second substrate pulls at the other to bend toward the same direction, thereby reducing warpage deviation of the overall electronic package. The present invention further provides a method for fabricating the electronic package.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: April 21, 2020
    Assignee: Silicon Precision Industries Co., Ltd.
    Inventors: Chi-Rui Wu, Fu-Tang Huang, Chia-Cheng Chen, Chun-Hsien Lin, Hsuan-Hao Mi, Yu-Cheng Pai
  • Patent number: 10600882
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate, and an interlayer dielectric disposed on the substrate which has agate structure therein. The gate structure further includes a gate electrode with a protruding portion, and a gate dielectric layer disposed between the gate electrode and the substrate. A spacer is disposed between the interlayer dielectric and the gate electrode. An insulating cap layer is disposed atop the gate electrode and encompasses the top and the sidewall of the protruding portion.
    Type: Grant
    Filed: October 11, 2015
    Date of Patent: March 24, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Yi-Wei Chen, Chun-Hsien Lin
  • Patent number: 10553534
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a first dielectric layer on a substrate, in which a first conductor is embedded within the first dielectric layer. Next, a second dielectric layer is formed on the first dielectric layer, part of the second dielectric layer is removed to form a contact hole, and a lateral etching process is conducted to expand the contact hole to form a funnel-shaped opening. Next, a metal layer is formed in the funnel-shaped opening, and the metal layer is planarized to form a second conductor.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: February 4, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Te Wei, Chun-Hsien Lin
  • Publication number: 20200020792
    Abstract: A method for fabricating a tunnel field effect transistor (TFET) includes the steps of providing a substrate and then forming an interfacial layer on the substrate. Preferably, the step of forming the interfacial layer includes the steps of: performing a plasma treatment process to inject a first gas containing nitrogen; injecting a second gas containing oxygen; and injecting a precursor to react with the first gas and the second gas for forming the interfacial layer.
    Type: Application
    Filed: September 25, 2019
    Publication date: January 16, 2020
    Inventors: An-Chi Liu, Chun-Hsien Lin
  • Patent number: 10512588
    Abstract: A sexual stimulating system with feedback control includes a physiological sensor, a sexual stimulator, and a processing module. The physiological sensor measures a physiological response of a user under sexual stimulation, and generates a sensor signal according to a result of the measurement of the physiological response. The sexual stimulator applies the sexual stimulation. The processing module is electrically connected to the physiological sensor and the sexual stimulator, receives the sensor signal, performs an analytical procedure upon the sensor signal for generating digital data, and generates a driving signal according to the digital data to control a degree of the sexual stimulation.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: December 24, 2019
    Assignee: NUWORLD CORPORATION
    Inventors: Jung-Hsi Hsieh, Jia-Hua Hong, Chun-Hsien Lin
  • Patent number: 10510884
    Abstract: A method for fabricating a semiconductor device is disclosed. A dummy gate is formed on a semiconductor substrate. The dummy gate has a first sidewall and a second sidewall opposite to the first sidewall. A low-k dielectric layer is formed on the first sidewall of the dummy gate and the semiconductor substrate. A spacer material layer is deposited on the low-k dielectric layer, the second sidewall of the dummy gate, and the semiconductor substrate. The spacer material layer and the low-k dielectric layer are etched to form a first spacer structure on the first sidewall and a second spacer structure on the second sidewall. A drain doping region is formed in the semiconductor substrate adjacent to the first spacer structure. A source doping region is formed in the semiconductor substrate adjacent to the second spacer structure.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: December 17, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chun-Hsien Lin
  • Publication number: 20190378985
    Abstract: A light-emitting diode display device is provided, including: a substrate, including a plurality of grooves, wherein an electrical contact is disposed in each of the grooves; and a plurality of light-emitting diodes, configured to be installed in the grooves, wherein each of the light-emitting diodes includes: a main body; and a first contact and a second contact, disposed on the main body, wherein the first contact and the second contact are respectively electrically connected to the substrate through the corresponding electrical contacts.
    Type: Application
    Filed: August 22, 2019
    Publication date: December 12, 2019
    Inventors: Chun-Hsien LIN, Ming-Chang LIN, Tzu-Min YAN, Tsau-Hua HSIEH, Tung-Kai LIU, Jui-Feng KO, Hui-Chieh WANG
  • Patent number: 10475892
    Abstract: A method for forming a tunneling field effect transistor is disclosed, which includes the following steps. First, a semiconductor substrate is provided. A source region is formed on the semiconductor substrate. A tunneling region having a sidewall and a top surface is formed on the source region. A drain region is formed on the tunneling region. A gate dielectric layer is then formed, covering the sidewall and the top surface of the tunneling region. A first metal layer is formed, covering the gate dielectric layer. Subsequently, an anisotropic etching process is performed to remove a portion of the first metal layer. After the anisotropic etching process, a second metal layer is fabricated to cover the remaining first metal layer and the gate dielectric layer.
    Type: Grant
    Filed: October 28, 2018
    Date of Patent: November 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: An-Chi Liu, Chun-Hsien Lin
  • Patent number: 10468517
    Abstract: A method for fabricating a tunnel field effect transistor (TFET) includes the steps of providing a substrate and then forming an interfacial layer on the substrate. Preferably, the step of forming the interfacial layer includes the steps of: performing a plasma treatment process to inject a first gas containing nitrogen; injecting a second gas containing oxygen; and injecting a precursor to react with the first gas and the second gas for forming the interfacial layer.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: November 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: An-Chi Liu, Chun-Hsien Lin
  • Patent number: 10446716
    Abstract: A display device includes a substrate, a first electrode, a second electrode, and a protective layer. The first electrode is disposed on the substrate. The second electrode has a first segment and a second segment. The first segment is located at a first side of the first electrode. The second segment is located at a second side of the first electrode. The second side is opposite to the first side. The protective layer overlaps the first segment and the second segment. The first segment has a length which is shorter than that of the second segment. The display device further includes a light-emitting element disposed on the substrate.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: October 15, 2019
    Assignee: INNOLUX CORPORATION
    Inventors: Chun-Hsien Lin, Jian-Jung Shih, Tsau-Hua Hsieh
  • Patent number: 10446752
    Abstract: A light-emitting diode display device includes a light-emitting diode and a substrate. The light-emitting diode includes a central axis, and the substrate includes a first connecting portion and a second connecting portion. The central axis is extended through the first connecting portion. The second connecting portion is disposed outside of the first connecting portion and is spaced apart from the first connecting portion by a distance which is greater than zero, and the first connecting portion and the second connecting portion are respectively electrically connected to the light-emitting diode.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: October 15, 2019
    Assignee: INNOLUX CORPORATION
    Inventors: Chun-Hsien Lin, Ming-Chang Lin, Tzu-Min Yan, Tsau-Hua Hsieh, Tung-Kai Liu, Jui-Feng Ko, Hui-Chieh Wang
  • Publication number: 20190279972
    Abstract: Provided is a display device, which includes a substrate, a transistor, a capacitor and a light emitting unit. The transistor and the capacitor are disposed on the substrate. The light emitting unit is disposed on the substrate and arranged corresponding to the capacitor. The light emitting unit includes a first light emitting diode. The first light emitting diode is electrically connected with the transistor and overlaps the capacitor. The display device has favorable space utilization, provides a repair function, or reduces the probability of failure.
    Type: Application
    Filed: May 23, 2019
    Publication date: September 12, 2019
    Applicant: Innolux Corporation
    Inventors: Chun-Hsien Lin, Shun-Yuan Hu, Tsau-Hua Hsieh, Li-Wei Mao, Tung-Kai Liu, Shu-Ming Kuo, Chih-Yung Hsieh
  • Publication number: 20190279909
    Abstract: The present invention provides a method for forming a semiconductor structure. The method including: Firstly, a substrate is provided, a first region and a second region are defined thereon, next, a gate dielectric layer and a work function metal layer are sequentially formed on the substrate within the first region and within the second region. Afterwards, a dielectric layer is formed on the work function metal layer within the second region, a hydrogen gas treatment is then performed on the substrate, and the work function metal layer is removed within the first region.
    Type: Application
    Filed: May 20, 2019
    Publication date: September 12, 2019
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Chun-Hsien Lin, Wei-Hao Huang, Kai-Teng Cheng
  • Publication number: 20190267385
    Abstract: A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a first doped region in a substrate; removing part of the first doped region to form a trench in the substrate; forming a gate structure in the trench; and forming a barrier structure between the gate structure and the first doped region.
    Type: Application
    Filed: May 8, 2019
    Publication date: August 29, 2019
    Inventors: Feng-Yi Chang, Chun-Hsien Lin, Fu-Che Lee
  • Publication number: 20190259762
    Abstract: A magnetic tunnel junction (MTJ) structure of a magnetic random access memory (MRAM) cell includes an insulation layer, a patterned MTJ film stack, an aluminum oxide protection layer, an interlayer dielectric, and a connection structure. The patterned MTJ film stack is disposed on the insulation layer. The aluminum oxide protection layer is disposed on a sidewall of the patterned MTJ film stack, and the aluminum oxide protection layer includes an aluminum film oxidized by an oxidation treatment. The interlayer dielectric covers the aluminum oxide protection layer and the patterned MTJ film stack. The connection structure penetrates the interlayer dielectric above the patterned MTJ film stack, and the connection structure is electrically connected to a topmost portion of the patterned MTJ film stack.
    Type: Application
    Filed: May 2, 2019
    Publication date: August 22, 2019
    Inventors: Hsiao-Pang Chou, Yu-Ru Yang, Chih-Chien Liu, Chao-Ching Hsieh, Chun-Hsien Lin
  • Publication number: 20190246921
    Abstract: The present invention provides a contactless-type sport training monitor method, comprising: selecting at least an image database to recognize a plurality of expressions in the image database; making pre-processing for the plurality of expressions: using a convolutional neural network as a feature point extraction model; acquiring a human image; tracking a first target region and a second target region in the human image; making chrominance-based rPPG trace extraction; using the deep level model to compare the second target region image; and to calculate a post-exercise heart rate recovery achievement ratio, to judge the Rating of Perceived Exertion, and judging whether the human body is under overtraining status or not.
    Type: Application
    Filed: July 20, 2018
    Publication date: August 15, 2019
    Applicant: National Chiao Tung University
    Inventors: Bing-Fei Wu, Chun-Hsien Lin, Po-Wei Huang, Tzu-Min Lin, Meng-Liang Chung
  • Publication number: 20190252259
    Abstract: The present invention provides a method for forming a semiconductor structure. The method including: Firstly, a substrate is provided, a first region and a second region are defined thereon, next, a gate dielectric layer and a work function metal layer are sequentially formed on the substrate within the first region and within the second region. Afterwards, a dielectric layer is formed on the work function metal layer within the second region, a hydrogen gas treatment is then performed on the substrate, and the work function metal layer is removed within the first region.
    Type: Application
    Filed: February 11, 2018
    Publication date: August 15, 2019
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Chun-Hsien Lin, Wei-Hao Huang, Kai-Teng Cheng
  • Publication number: 20190251336
    Abstract: A facial expression recognition training system includes a training module, feature database, a capturing module, a recognition module and an adjusting module. The training module trains a facial expression feature capturing model according to known face images. The feature database stores known facial expression features of the known face images. The capturing module continuously captures first face images, and the facial expression feature capturing model outputs facial expression features of the first face images according to the first face images. The recognition module compares the facial expression features and the known facial expression features, and fit the facial expression features to the first known facial expression features that is one kind of the known facial expression feature accordingly. The adjusting module adjusts the facial expression feature capturing model to reduce the differences between the facial expression features and the known facial expression features.
    Type: Application
    Filed: January 23, 2019
    Publication date: August 15, 2019
    Inventors: Bing-Fei WU, Chun-Hsien LIN, Meng-Liang CHUNG