Abstract: A semiconductor device includes a substrate having an input/output (I/O) region, an one time programmable (OTP) capacitor region, and a core region, a first metal gate disposed on the I/O region, a second metal gate disposed on the core region, and a third metal gate disposed on the OTP capacitor region. Preferably, the first metal gate includes a first high-k dielectric layer, the second metal gate includes a second high-k dielectric layer, and the first high-k dielectric layer and the second high-k dielectric layer include an I-shape.

Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.

Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.

Abstract: A one-time programmable (OTP) memory cell includes a substrate having a first conductivity type and having an active area surrounded by an isolation region, a transistor disposed on the active area, and a capacitor disposed on the active area and electrically coupled to the transistor. The capacitor comprises a diffusion region of a second conductivity type in the substrate, a metallic film in direct contact with the active area, a capacitor dielectric layer on the metallic film, and a metal gate surrounded by the capacitor dielectric layer. The diffusion region and the metallic film constitute a capacitor bottom plate.

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, an inter-metal dielectric (IMD) layer on the substrate, a MTJ in the IMD layer on the MTJ region, a first metal interconnection in the IMD layer on the logic region, and protrusions adjacent to two sides of the first metal interconnection. Preferably, the MTJ further includes a bottom electrode, a fixed layer, a barrier layer, a free layer, and a top electrode.

Abstract: An electronic device including a panel, a Chip on Film and a flexible circuit board is disclosed. The panel includes a first gate driver, a switch transistor and a driving transistor. An output terminal of the switch transistor is coupled to a control terminal of the driving transistor. The first gate driver is used for receiving an AC signal and a DC signal and outputting a control signal to a control terminal of the switch transistor. The Chip on Film is electrically connected to the panel and used for transmitting a data signal to an input terminal of the switch transistor and transmitting the AC signal to the first gate driver. The flexible circuit board is electrically connected to the panel and used for transmitting a power signal to an input terminal of the driving transistor and transmitting the DC signal to the first gate driver.

Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.

Abstract: Abstract of Disclosure An electronic device includes a diode, a driving circuit, a first signal line, a second signal line, a first electrostatic protection circuit and a second electrostatic protection circuit. The diode has a first end and a second end. The first signal line is coupled between the first end and the driving circuit. The second signal line is coupled between the second end and the driving circuit. The first electrostatic protection circuit is coupled to the first signal line. The second electrostatic protection circuit is coupled to the second signal line.

Abstract: An electronic device is provided in this disclosure. In some embodiments, the electronic device includes a first substrate and a second substrate adjacent to the first substrate. In some embodiments, the electronic device includes a plurality of organic light emitting diodes, a filter layer, and a third substrate. At least a part of the plurality of organic light emitting diodes are disposed on the first substrate. The filter layer is disposed at least on the second substrate. The third substrate is disposed corresponding to the first substrate and the second substrate. The plurality of organic light emitting diodes and the filter layer are disposed under the third substrate.

Abstract: An electronic device is provided, the electronic device includes a driving substrate, the driving substrate includes a plurality of circular grooves and a plurality of rectangular grooves, a plurality of disc-shaped light-emitting units, at least one disc-shaped light-emitting unit is disposed in at least one circular groove, and the at least one disc-shaped light-emitting unit includes an alignment element positioned on a top surface of the at least one disc-shaped light-emitting unit, a diameter of the at least one disc-shaped light-emitting unit is defined as R, a diameter of the alignment element is defined as r, a width of at least one rectangular groove among the rectangular grooves is defined as w, and a height of the at least one rectangular groove is defined as H, and the at least one disc-shaped light-emitting unit and the at least one rectangular groove satisfy the condition of (R+r)/2>(w2+H2)1/2.

Abstract: An electronic device is provided, the electronic device includes a driving substrate, the driving substrate includes a plurality of first grooves and a plurality of second grooves, the first grooves and the second grooves have different sizes, at least one first electronic component of the plurality of first electronic components is disposed in one of the plurality of first grooves, at least one second electronic component of the plurality of second electronic components is disposed in one of the plurality of second grooves, a maximum length passing through a center of a bottom surface of the at least one first electronic component is defined as L1, a bottom length of one side of at least one second groove among the second grooves is defined as L2, and the at least one first electronic component and the at least one second groove satisfy the condition of L1>L2.

Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.

Abstract: A semiconductor device for internet of things (IoT) device includes a substrate having an array region defined thereon and a ring of dummy pattern surrounding the array region. Preferably, the ring of dummy pattern includes a plurality of magnetic tunneling junctions (MTJs) and a ring of metal interconnect pattern overlapping the MTJs and surrounding the array region. The semiconductor device further includes a gap between the array region and the ring of dummy pattern.

Abstract: An electronic device includes a conductive structure, a first insulation layer and a second insulation layer. The first insulation layer is disposed on the conductive structure. The second insulation layer is disposed on the first insulation layer. The first insulation layer includes a first hole, and the first hole overlaps a part of the conductive structure. The second insulation layer includes a second hole, and the first hole and the second hole at least partially overlap. A width of the second hole is less than a width of the first hole.

Abstract: The disclosure provides an electronic device including a substrate, an electronic element, a driving element, a first trace, a second trace, a conductive pattern, and an electrostatic discharge protection element. The substrate includes a first surface, a second surface, and a third surface. The third surface connects to the first surface and the second surface. The electronic element is disposed on the first surface. The driving element is disposed on the second surface. The first traces are disposed on the first surface. The second traces are disposed on the second surface and are electrically connected to the driving element, and the corresponding first traces are electrically connected to the corresponding second traces. The conductive pattern is electrically connected to the driving element and receives a grounding voltage or is floating. The electrostatic discharge protection element is disposed on the first surface and is electrically connected to the driving element.

Abstract: An electronic device is provided in this disclosure. In some embodiments, the electronic device includes two display panels, a first filling element, and a second filling element. The two display panels adjoin each other. The first filling element and the second filling element are disposed between the two display panels, and a material of the first filling element is different from a material of the second filling element. In some embodiments, the electronic device includes a protection substrate, two light emitting plates, and a filling element. The two light emitting plates adjoin each other. The protection substrate is disposed corresponding to the two light emitting plates, and the two light emitting plates emit light towards the protection substrate. The filling element is disposed between the two light emitting plates.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a first inter-metal dielectric (IMD) layer on a substrate, forming a first trench and a second trench in the first IMD layer, forming a bottom electrode in the first trench and the second trench, forming a ferroelectric (FE) layer on the bottom electrode, and then forming a top electrode on the FE layer to form a ferroelectric random access memory (FeRAM).

Abstract: An electronic device with an active region comprising a substrate; a first conducting layer, disposed on the substrate, comprising a first pad in the active region; a second conducting layer, disposed on the first conducting layer, comprising a second pad in the active region; a first electronic component, disposed on the first pad, and electronically connected to the first pad; and a second electronic component, disposed on the second pad, and electronically connected to the second pad.

Abstract: A semiconductor device for internet of things (IoT) device includes a substrate having an array region defined thereon and a ring of dummy pattern surrounding the array region. Preferably, the ring of dummy pattern includes a plurality of magnetic tunneling junctions (MTJs) and a ring of metal interconnect pattern overlapping the MTJs and surrounding the array region. The semiconductor device further includes a gap between the array region and the ring of dummy pattern.

Abstract: A manufacturing method includes providing a first substrate including a circuit layer and an electronic element disposed on the circuit layer, providing a second substrate, bonding the first substrate and the second substrate to form an electronic module, cutting the electronic module, forming a wire on a first surface exposed after cutting the electronic module and on a second surface of the electronic module, wherein the first surface is adjacent to the second surface and the wire is electrically connected to the circuit layer, and disposing a driving element on the second surface of the electronic module to be electrically connected to the wire.