Patents by Inventor Chun-Hsien Lin

Chun-Hsien Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Digital device using three states
    Patent number: 11196247
    Abstract: A digital device is provided. The digital device uses three states, including a ground (GND) state, a voltage (VDD) state, and a FLOAT state. On designing a chip, two storage units and a pad circuit are set inside; the pad circuit comprises a current limiter and two switches; and less ports contained are required than the conventional. That is, one port obtains three states. As comparing to the conventional having only two states, the present invention uses the port connected with two storage units in the pad circuit for obtaining the three states; a circuit featuring “pull up” and “pull down” is used to identify the state of connection of the port; and the port determines a plurality of definitions through the three states of GND, VDD and FLOAT. Thus, a pad is saved for reducing the space and cost of the chip.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: December 7, 2021
    Assignees: Dyna Image Corporation, Lite-On Semiconductor Corporation
    Inventors: Peng-Han Chan, Chun-Hsien Lin, Sheng-Cheng Lee, Wen-Sheng Lin, Yu-Cheng Su
  • DISPLAY PANEL AND SPLICED DISPLAY
    Publication number: 20210366371
    Abstract: The disclosure provides a display panel and a spliced display device. The display panel includes a substrate, an array circuit, and a power supply circuit. The substrate includes a top surface, a bottom surface, and a side surface located between the top surface and the bottom surface. The array circuit is disposed on the top surface. Power is supplied to the array circuit through the power supply circuit. The power supply circuit has a power input terminal. The power input terminal corresponds to at least two distribution terminals. The at least two distribution terminals are disposed on the side surface and distribute the power to different portions of the array circuit.
    Type: Application
    Filed: May 4, 2021
    Publication date: November 25, 2021
    Applicant: Innolux Corporation
    Inventor: Chun-Hsien Lin
  • ELECTRONIC DEVICE
    Publication number: 20210335761
    Abstract: An electronic device is provided in this disclosure. In some embodiments, the electronic device includes two display panels, a first filling element, and a second filling element. The two display panels adjoin each other. The first filling element and the second filling element are disposed between the two display panels, and a material of the first filling element is different from a material of the second filling element. In some embodiments, the electronic device includes a protection substrate, two light emitting plates, and a filling element. The two light emitting plates adjoin each other. The protection substrate is disposed corresponding to the two light emitting plates, and the two light emitting plates emit light towards the protection substrate. The filling element is disposed between the two light emitting plates.
    Type: Application
    Filed: November 30, 2020
    Publication date: October 28, 2021
    Inventors: Wan-Ling Huang, Chun-Hsien Lin, Yi-An Chen, Tsau-Hua Hsieh
  • ELECTRONIC DEVICE
    Publication number: 20210298210
    Abstract: An electronic device is provided, which is for coupling to another electronic device in a side-by-side manner, and the electronic device includes a substrate, a first thermal dissipation sheet and a thermal dissipation element. The substrate includes a first surface and a second surface. The first thermal dissipation sheet is disposed on the first surface. The thermal dissipation element is disposed on the substrate. The first thermal dissipation sheet is disposed between the thermal dissipation element and the substrate, and the thermal dissipation element at least partially overlaps the first thermal dissipation sheet.
    Type: Application
    Filed: February 22, 2021
    Publication date: September 23, 2021
    Inventors: Wan-Ling HUANG, Tzu-Yuan LIN, Geng-Fu CHANG, Chun-Hsien LIN, Shu-Ming KUO, Jui-Feng KO, Tsau-Hua HSIEH
  • DISPLAY DEVICE
    Publication number: 20210280567
    Abstract: A display device includes a substrate, a first signal line disposed on the substrate, and a first pixel including a first transistor having a gate electrode, a source electrode and a drain electrode, wherein the source electrode is electrically connected to the first signal line. The display device includes a fan-out line electrically connected to the first signal line, wherein the fan-out line partially overlaps the first pixel and is formed in a layer different from layers of the gate electrode, the source electrode and the drain electrode.
    Type: Application
    Filed: November 22, 2020
    Publication date: September 9, 2021
    Inventors: Chun-Hsien Lin, Tsau-Hua Hsieh
  • DISPLAY DEVICE
    Publication number: 20210233820
    Abstract: A display device includes a substrate, a light-emitting element, and a transistor. The substrate has a top surface. The light-emitting element is disposed on the substrate, and includes a first electrode and a second electrode. The transistor is disposed on the substrate and electrically connected to the light-emitting element. The transistor includes a gate electrode and a semiconductor layer. The semiconductor layer includes an overlapping portion overlapped with the gate electrode. The first electrode and the second electrode of the light-emitting element do not overlap with the overlapping portion along a direction perpendicular to the top surface of the substrate.
    Type: Application
    Filed: April 13, 2021
    Publication date: July 29, 2021
    Inventors: Tung-Kai LIU, Tsau-Hua HSIEH, Wei-Cheng CHU, Chun-Hsien LIN, Chandra LIUS, Ting-Kai HUNG, Kuan-Feng LEE, Ming-Chang LIN, Tzu-Min YAN, Hui-Chieh WANG
  • MAGNETORESISTIVE RANDOM ACCESS MEMORY
    Publication number: 20210210675
    Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, an inter-metal dielectric (IMD) layer on the substrate, a MTJ in the IMD layer on the MTJ region, a first metal interconnection in the IMD layer on the logic region, and protrusions adjacent to two sides of the first metal interconnection. Preferably, the MTJ further includes a bottom electrode, a fixed layer, a barrier layer, a free layer, and a top electrode.
    Type: Application
    Filed: March 23, 2021
    Publication date: July 8, 2021
    Inventors: An-Chi Liu, Chun-Hsien Lin
  • People-flow analysis system and people-flow analysis method
    Patent number: 11017241
    Abstract: A people-flow analysis system includes an image source, a computing device, and a host. The image source captures a first image and a second image. The computing device is connected to the image source. The computing device identifies the first image according to a data set to generate a first detecting image. The first detecting image has a position box corresponding to a pedestrian in the first image. The computing device generates a tracking image according to the data set and a difference between the first detecting image and the second image. The tracking image has another position box corresponding to a pedestrian in the second image. The host is connected to the computing device and generates a people-flow list according to the first detecting image and the tracking image.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: May 25, 2021
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Bing-Fei Wu, Chun-Hsien Lin, Po-Wei Huang, Meng-Liang Chung
  • Display device and method of manufacturing the display device
    Patent number: 11004753
    Abstract: A display device includes a substrate, a light-emitting element, and a transistor. The substrate has a top surface. The light-emitting element is disposed on the substrate. The transistor is disposed on the substrate, and includes a drain electrode, a gate electrode, and a semiconductor layer. The drain electrode is electrically connected to the light-emitting element. The semiconductor layer includes an overlapping portion overlapped with the gate electrode. The light-emitting element does not overlap with the overlapping portion along a direction perpendicular to the top surface of the substrate.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: May 11, 2021
    Assignee: INNOLUX CORPORATION
    Inventors: Tung-Kai Liu, Tsau-Hua Hsieh, Wei-Cheng Chu, Chun-Hsien Lin, Chandra Lius, Ting-Kai Hung, Kuan-Feng Lee, Ming-Chang Lin, Tzu-Min Yan, Hui-Chieh Wang
  • Magnetoresistive random access memory
    Patent number: 10991875
    Abstract: A semiconductor device includes: a substrate having a magnetic tunneling junction (MTJ) region and a logic region; an inter-metal dielectric (IMD) layer on the substrate; a first metal interconnection in the IMD layer on the logic region; and protrusions adjacent to two sides of the first metal interconnection. Preferably, the first metal interconnection further includes a via conductor and a trench conductor and the protrusions includes a first protrusion on one side of the via conductor and a second protrusion on another side of the via conductor.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: April 27, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: An-Chi Liu, Chun-Hsien Lin
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20210118750
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.
    Type: Application
    Filed: December 27, 2020
    Publication date: April 22, 2021
    Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
  • HIGH ELECTRON MOBILITY TRANSISTOR
    Publication number: 20210083073
    Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a gate electrode on the barrier layer, a first passivation layer adjacent to two sides of the gate electrode, and a p-type semiconductor layer between the gate electrode and the barrier layer. Preferably, a corner of the p-type semiconductor layer contacting a sidewall of the first passivation layer includes a first curve, and a bottom surface of the p-type semiconductor layer directly on the first passivation layer includes a second curve.
    Type: Application
    Filed: October 14, 2019
    Publication date: March 18, 2021
    Inventors: An-Chi Liu, Chun-Hsien Lin
  • Method for low-current oscillatory circuit with wide operation voltage and temperature compensation
    Patent number: 10951163
    Abstract: A smart method is provided for a low-current oscillatory circuitry. The circuitry comprises an oscillator and a microcontroller unit (MCU). The oscillator comprises a proportional-to-absolute-temperature circuit connecting to a low-voltage regulator. The low-voltage regulator connects to a PMOS diode array and a delay unit circuit. The PMOS diode array connects to the MCU. The delay unit circuit connects to the MCU and a voltage converter. The method includes a normal temperature compensation algorithm; a smart learning algorithm of extra-high temperature compensation; and an ultra-high temperature compensation algorithm. Thus, clock variations are compensated; output frequency is stable and not affected by voltage or temperature variations; and process variations are suppressed. When process variations appear, there are not be too many errors generated.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: March 16, 2021
    Assignees: Dyna Image Corporation, Lite-On Semiconductor Corp.
    Inventors: Sheng-Cheng Lee, Wen-Sheng Lin, Yu-Cheng Su, Chun-Hsien Lin, Peng-Han Chan
  • Display device
    Patent number: 10937775
    Abstract: Provided is a display device, which includes a substrate, a transistor, a capacitor and a light emitting unit. The transistor and the capacitor are disposed on the substrate. The light emitting unit is disposed on the substrate and arranged corresponding to the capacitor. The light emitting unit includes a first light emitting diode. The first light emitting diode is electrically connected with the transistor and overlaps the capacitor. The display device has favorable space utilization, provides a repair function, or reduces the probability of failure.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: March 2, 2021
    Assignee: Innolux Corporation
    Inventors: Chun-Hsien Lin, Shun-Yuan Hu, Tsau-Hua Hsieh, Li-Wei Mao, Tung-Kai Liu, Shu-Ming Kuo, Chih-Yung Hsieh
  • METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
    Publication number: 20210057551
    Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.
    Type: Application
    Filed: November 6, 2020
    Publication date: February 25, 2021
    Inventors: Po-Chang Lin, Bo-Han Huang, Chih-Chung Chen, Chun-Hsien Lin, Shih-Hung Tsai, Po-Kuang Hsieh
  • BURIED WORD LINE OF A DYNAMIC RANDOM ACCESS MEMORY AND METHOD FOR FABRICATING THE SAME
    Publication number: 20210043632
    Abstract: A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a first doped region in a substrate; removing part of the first doped region to form a trench in the substrate; forming a gate structure in the trench; and forming a barrier structure between the gate structure and the first doped region.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 11, 2021
    Inventors: Feng-Yi Chang, Chun-Hsien Lin, Fu-Che Lee
  • Light sensor device controlled with dual-mode master-and-slave MCU application
    Patent number: 10915079
    Abstract: A light sensor device is provided. It is controlled with a dual-mode master-and-slave microcontroller unit (MCU) application. An MCU is embedded into a light sensor chip. The original dual-mode master-and-slave dual-CPU architectures are combined to be operated as a single-CPU architecture. Since the original circuit pin design is followed, it is possible to be compatible with the old circuit design. The present invention uses a single-CPU architecture to directly control light sensors. Through the configuration of RAM, an inter-integrated circuit bus (I2C I/F) can be redirected to an internal non-volatile memory to switch the operational mode of the light sensor chip from a slave machine to a host machine which switches off the interrupt pin and, then, turns to a GPIO pin. Thus, the present invention provides a simple single-CPU architecture with easy use and effectively-lowered cost.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: February 9, 2021
    Assignees: Dyna Image Corporation, Lite-On Semiconductor Corporation
    Inventors: Chun-Hsien Lin, Peng-Han Chan, Wen-Sheng Lin, Yu-Cheng Su, Sheng-Cheng Lee
  • Display device and driving method thereof having a display area in a peripheral region
    Patent number: 10909914
    Abstract: A semiconductor device includes a first display unit and a second display unit. The first display unit includes a first substrate, first light-emitting units, and a first gate driver circuit. The first substrate includes a first display region. The first substrate has a first side and a second side. The first light-emitting units are disposed in the first display region. The first gate driver circuit is disposed in the first display region. The second display unit is adjacent to the first display unit. The second display unit includes a second substrate. The second substrate includes a second display region, second light-emitting units, and a second gate driver circuit. The second substrate has a third side and a fourth side. The second light-emitting units are disposed in the second display region. A second gate driver circuit is disposed in the second display region.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: February 2, 2021
    Assignee: INNOLUX CORPORATION
    Inventors: Geng-Fu Chang, Jui-Feng Ko, Tsau-Hua Hsieh, Chun-Hsien Lin, Jian-Jung Shih
  • Semiconductor device and method for fabricating the same
    Patent number: 10910277
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: February 2, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Jung Chuang, Po-Jen Chuang, Yu-Ren Wang, Chi-Mao Hsu, Chia-Ming Kuo, Guan-Wei Huang, Chun-Hsien Lin
  • Method for fabricating tunneling field effect transistor having interfacial layer containing nitrogen
    Patent number: 10886395
    Abstract: A method for fabricating a tunnel field effect transistor (TFET) includes the steps of providing a substrate and then forming an interfacial layer on the substrate. Preferably, the step of forming the interfacial layer includes the steps of: performing a plasma treatment process to inject a first gas containing nitrogen; injecting a second gas containing oxygen; and injecting a precursor to react with the first gas and the second gas for forming the interfacial layer.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: January 5, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: An-Chi Liu, Chun-Hsien Lin