Patents by Inventor Chun-Lang Chen

Chun-Lang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9122175
    Abstract: A system and method for repairing a photolithographic mask is provided. An embodiment comprises forming a shielding layer over an absorbance layer on a substrate. Once the shielding layer is in place, the absorbance layer may be repaired using, e.g., an e-beam process to initiate a reaction to repair a defect in the absorbance layer, with the shielding layer being used to shield the remainder of the absorbance layer from undesirable etching during the repair process.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: September 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen, Jong-Yuh Chang, Boming Hsu, Tran-Hui Shen
  • Publication number: 20150227038
    Abstract: In some embodiments, a mask patterning system includes an electronic memory configured to store an integrated circuit mask layout. A computation tool determines a number of radiation shots to be used to write the integrated circuit mask layout to a physical mask. The computation tool also determines a scaling factor which accounts for expected thermal expansion of the physical mask due to the number of radiation shots used in writing the integrated circuit mask layout to the physical mask. An ebeam or laser writing tool writes the integrated circuit mask layout to the physical mask based on the scaling factor and by using the number of radiation shots.
    Type: Application
    Filed: April 27, 2015
    Publication date: August 13, 2015
    Inventors: Chih-Chiang Tu, Chun-Lang Chen, Jong-Yuh Chang, Chien-Chih Chen, Chen-Shao Hsu
  • Patent number: 9057961
    Abstract: Structure of mask blanks and masks, and methods of making masks are disclosed. The new mask blank and mask comprise a tripe etching stop layer to prevent damages to the quartz substrate when the process goes through etching steps three times. The triple etching stop layer may comprise a first sub-layer of tantalum containing nitrogen (TaN), a second sub-layer of tantalum containing oxygen (TaO), and a third sub-layer of TaN. Alternatively, the triple etching stop layer may comprise a first sub-layer of SiON material, a second sub-layer of TaO material, and a third sub-layer of SiON material. Another alternative may be one layer of low etching rate MoxSiyONz material which can prevent damages to the quartz substrate when the process goes through etching steps three times. The island mask is defined on the mask blank by using various optical proximity correction rules.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: June 16, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chiang Tu, Hsin-Chang Lee, Jong-Yuh Chang, Chia-Jen Chen, Chun-Lang Chen
  • Publication number: 20150132685
    Abstract: A first embodiment is a lithography mask comprising a transparent substrate and a first molybdenum silicon nitride (MoxSiyNz) layer. The first MoxSiyNz layer is over the transparent substrate. A percentage of molybdenum (x) of the first MoxSiyNz layer is between 1 and 2. A percentage of silicon (y) of the first MoxSiyNz layer is between 50 and 55. A percentage of nitride (z) of the first MoxSiyNz layer is between 40 and 50. The first MoxSiyNz layer has an opening therethrough.
    Type: Application
    Filed: December 2, 2014
    Publication date: May 14, 2015
    Inventors: Chue San Yoo, Chun-Lang Chen
  • Patent number: 9017903
    Abstract: Some embodiments of the present disclosure relate to a method of patterning a workpiece with a mask, wherein a scale factor between a geometry of the mask and a corresponding target shape of the mask is determined. The scale factor results from thermal expansion of the mask and geometry due to heating of the mask during exposure to radiation by an electron beam (e-beam) in the mask manufacturing process. A number of radiation pulses necessary to dispose the geometry on the mask is determined. A scale factor for the mask is then determined from the number of pulses. The target shape is then generated on the mask by re-scaling the geometry according to the scale factor prior to mask manufacturing. This method compensates for thermal deformation due to e-beam heating to improve OVL variability in advanced technology nodes.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: April 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen, Jong-Yuh Chang, Chien-Chih Chen, Chen-Shao Hsu
  • Patent number: 8999611
    Abstract: Some embodiments relate a method of forming a photomask for a deep ultraviolet photolithography process (e.g., having an exposing radiation with a wavelength of 193 nm). The method provides a mask blank for a deep ultraviolet photolithography process. The mask blank has a transparent substrate, an amorphous isolation layer located over the transparent substrate, and a photoresist layer located over the amorphous isolation layer. The photoresist layer is patterned by selectively removing portions of the photoresist layer using a beam of electrons. The amorphous isolation layer is subsequently etched according to the patterned photoresist layer to form one or more mask openings. The amorphous isolation layer isolates electrons backscattered from the beam of electrons from the photoresist layer during patterning, thereby mitigating CD and overlay errors caused by backscattered electrons.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen, Jong-Yuh Chang, Chien-Chih Chen, Chen-Shao Hsu
  • Patent number: 8981557
    Abstract: A photovoltaic cell manufacturing method is disclosed. Methods include manufacturing a photovoltaic cell having a selective emitter and buried contact (electrode) structure utilizing nanoimprint technology. The methods include providing a semiconductor substrate having a first surface and a second surface opposite the first surface; forming a first doped region in the semiconductor substrate adjacent to the first surface; performing a nanoimprint process and an etching process to form a trench in the semiconductor substrate, the trench extending into the semiconductor substrate from the first surface; forming a second doped region in the semiconductor substrate within the trench, the second doped region having a greater doping concentration than the first doped region; and filling the trench with a conductive material. The nanoimprint process uses a mold to define a location of an electrode line layout.
    Type: Grant
    Filed: September 17, 2012
    Date of Patent: March 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen
  • Publication number: 20150024306
    Abstract: Some embodiments of the present disclosure relate to a method of patterning a workpiece with a mask, wherein a scale factor between a geometry of the mask and a corresponding target shape of the mask is determined. The scale factor results from thermal expansion of the mask and geometry due to heating of the mask during exposure to radiation by an electron beam (e-beam) in the mask manufacturing process. A number of radiation pulses necessary to dispose the geometry on the mask is determined. A scale factor for the mask is then determined from the number of pulses. The target shape is then generated on the mask by re-scaling the geometry according to the scale factor prior to mask manufacturing. This method compensates for thermal deformation due to e-beam heating to improve OVL variability in advanced technology nodes.
    Type: Application
    Filed: July 22, 2013
    Publication date: January 22, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen, Jong-Yuh Chang, Chien-Chih Chen, Chen-Shao Hsu
  • Patent number: 8921014
    Abstract: A first embodiment is a lithography mask comprising a transparent substrate and a first molybdenum silicon nitride (MoxSiyNz) layer. The first MoxSiyNz layer is over the transparent substrate. A percentage of molybdenum (x) of the first MoxSiyNz layer is between 1 and 2. A percentage of silicon (y) of the first MoxSiyNz layer is between 50 and 55. A percentage of nitride (z) of the first MoxSiyNz layer is between 40 and 50. The first MoxSiyNz layer has an opening therethrough.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chue-San Yoo, Chun-Lang Chen
  • Publication number: 20140335446
    Abstract: Structure of mask blanks and masks, and methods of making masks are disclosed. The new mask blank and mask comprise a tripe etching stop layer to prevent damages to the quartz substrate when the process goes through etching steps three times. The triple etching stop layer may comprise a first sub-layer of tantalum containing nitrogen (TaN), a second sub-layer of tantalum containing oxygen (TaO), and a third sub-layer of TaN. Alternatively, the triple etching stop layer may comprise a first sub-layer of SiON material, a second sub-layer of TaO material, and a third sub-layer of SiON material. Another alternative may be one layer of low etching rate MoxSiyONz material which can prevent damages to the quartz substrate when the process goes through etching steps three times. The island mask is defined on the mask blank by using various optical proximity correction rules.
    Type: Application
    Filed: July 21, 2014
    Publication date: November 13, 2014
    Inventors: Chih-Chiang Tu, Hsin-Chang Lee, Jong-Yuh Chang, Chia-Jen Chen, Chun-Lang Chen
  • Patent number: 8882304
    Abstract: An illuminating device includes a substrate, an illuminating element, at least one barricade and at least one cover layer. The illuminating element is disposed on the substrate. The barricade is protruded from a surface of the substrate and disposed around the illuminating element continuously or discontinuously to form a first accommodating area. The cover layer is disposed in the first accommodating area for covering the illuminating element.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: November 11, 2014
    Assignee: Delta Electronics, Inc.
    Inventors: Hsiang-Chen Wu, Ching-Chuan Shiue, Chun-Lang Chen, Chun-Huang Cheng
  • Publication number: 20140273301
    Abstract: An apparatus for increasing the uniformity in a critical dimension of chemical vapor deposition and etching during substrate processing, comprising a plurality of gas injectors for admitting a processing gas into an etching chamber. Each gas injector of the plurality of gas injectors is disposed along a track within the etching chamber and moveable along the track. Further, each gas injector is coupled with a throttling valve or nozzle to permit adjustment of processing gas flow rate. A method for increasing the uniformity in a critical dimension of chemical vapor deposition and etching during substrate processing includes performing a chemical deposition or etch using the plurality of moveable and adjustable gas injectors and measuring the critical dimension uniformity. Adjustments to the location of at least one gas injector or the processing gas flow rate to at least one gas injector are made to increase critical dimension uniformity.
    Type: Application
    Filed: November 26, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzung-Shiun LU, Chun-Lang CHEN, Shih-Hao YANG, Jong-Yuh CHANG
  • Publication number: 20140255825
    Abstract: Some embodiments relate a method of forming a photomask for a deep ultraviolet photolithography process (e.g., having an exposing radiation with a wavelength of 193 nm). The method provides a mask blank for a deep ultraviolet photolithography process. The mask blank has a transparent substrate, an amorphous isolation layer located over the transparent substrate, and a photoresist layer located over the amorphous isolation layer. The photoresist layer is patterned by selectively removing portions of the photoresist layer using a beam of electrons. The amorphous isolation layer is subsequently etched according to the patterned photoresist layer to form one or more mask openings. The amorphous isolation layer isolates electrons backscattered from the beam of electrons from the photoresist layer during patterning, thereby mitigating CD and overlay errors caused by backscattered electrons.
    Type: Application
    Filed: March 7, 2013
    Publication date: September 11, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen, Jong-Yuh Chang, Chien-Chih Chen, Chen-Shao Hsu
  • Patent number: 8785083
    Abstract: Structure of mask blanks and masks, and methods of making masks are disclosed. The new mask blank and mask comprise a tripe etching stop layer to prevent damages to the quartz substrate when the process goes through etching steps three times. The triple etching stop layer may comprise a first sub-layer of tantalum containing nitrogen (TaN), a second sub-layer of tantalum containing oxygen (TaO), and a third sub-layer of TaN. Alternatively, the triple etching stop layer may comprise a first sub-layer of SiON material, a second sub-layer of TaO material, and a third sub-layer of SiON material. Another alternative may be one layer of low etching rate MoxSiyONz material which can prevent damages to the quartz substrate when the process goes through etching steps three times. The island mask is defined on the mask blank by using various optical proximity correction rules.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: July 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chiang Tu, Hsin-Chang Lee, Jong-Yuh Chang, Chia-Jen Chen, Chun-Lang Chen
  • Publication number: 20140199787
    Abstract: Provided is a method for creating a mask blank that includes a stop layer. The stop layer is optically compatible and process compatible with other layers included as part of the mask blanks. Such blanks may include EUV, phase-shifting, or OMOG masks. The stop layer includes molybdenum, silicon, and nitride in a proportion that allows for compatibility and aids in detection by a residual gas analyzer. Provided is also a method for the patterning of mask blanks with a stop layer, particularly the method for removing semi-transparent residue defects that may occur due to problems in prior mask creation steps. The method involves the detection of included materials with a residual gas analyzer. Provided is also a mask blank structure which incorporates the compatible stop layer.
    Type: Application
    Filed: March 26, 2014
    Publication date: July 17, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen, Boming Hsu, Tran-Hui Shen
  • Patent number: 8715890
    Abstract: Provided is a method for creating a mask blank that include a stop layer. The stop layer is optically compatible and process compatible with other layers included as part of the mask blanks. Such blanks may include EUV, phase-shifting, or OMOG masks. The stop layer includes molybdenum, silicon, and nitride in a proportion that allows for compatibility and aids in detection by a residual gas analyzer. Provided is also a method for the patterning of mask blanks with a stop layer, particularly the method for removing semi-transparent residue defects that may occur due to problems in prior mask creation steps. The method involves the detect of included materials with a residual gas analyzer. Provided is also a mask blank structure which incorporates the compatible stop layer.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: May 6, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen, Boming Hsu, Tran-Hui Shen
  • Publication number: 20140106262
    Abstract: A system and method for repairing a photolithographic mask is provided. An embodiment comprises forming a shielding layer over an absorbance layer on a substrate. Once the shielding layer is in place, the absorbance layer may be repaired using, e.g., an e-beam process to initiate a reaction to repair a defect in the absorbance layer, with the shielding layer being used to shield the remainder of the absorbance layer from undesirable etching during the repair process.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 17, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen, Jong-Yuh Chang, Boming Hsu, Tran-Hui Shen
  • Publication number: 20140014176
    Abstract: A photovoltaic device manufacturing method is disclosed. Methods include manufacturing a photovoltaic cell using nanoimprint technology to define individual cell units of the photovoltaic device. The methods can include providing a substrate; forming a first conductive layer over the substrate; forming first grooves in the first conductive layer using a nanoimprint and etching process; forming an absorption layer over the first conductive layer, the absorption layer filling in the first grooves; forming second grooves in the absorption layer using a nanoimprint process; forming a second conductive layer over the absorption layer, the second conductive layer filling in the second grooves; and forming third grooves in the second conductive layer and the absorption layer, thereby defining a photovoltaic cell unit.
    Type: Application
    Filed: September 20, 2013
    Publication date: January 16, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chiang TU, Chun-Lang CHEN
  • Publication number: 20130323625
    Abstract: Structure of mask blanks and masks, and methods of making masks are disclosed. The new mask blank and mask comprise a tripe etching stop layer to prevent damages to the quartz substrate when the process goes through etching steps three times. The triple etching stop layer may comprise a first sub-layer of tantalum containing nitrogen (TaN), a second sub-layer of tantalum containing oxygen (TaO), and a third sub-layer of TaN. Alternatively, the triple etching stop layer may comprise a first sub-layer of SiON material, a second sub-layer of TaO material, and a third sub-layer of SiON material. Another alternative may be one layer of low etching rate MoxSiyONz material which can prevent damages to the quartz substrate when the process goes through etching steps three times. The island mask is defined on the mask blank by using various optical proximity correction rules.
    Type: Application
    Filed: June 1, 2012
    Publication date: December 5, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chiang Tu, Hsin-Chang Lee, Jong-Yuh Chang, Chia-Jen Chen, Chun-Lang Chen
  • Patent number: 8563351
    Abstract: A photovoltaic device manufacturing method is disclosed. Methods include manufacturing a photovoltaic cell using nanoimprint technology to define individual cell units of the photovoltaic device. The methods can include providing a substrate; forming a first conductive layer over the substrate; forming first grooves in the first conductive layer using a nanoimprint and etching process; forming an absorption layer over the first conductive layer, the absorption layer filling in the first grooves; forming second grooves in the absorption layer using a nanoimprint process; forming a second conductive layer over the absorption layer, the second conductive layer filling in the second grooves; and forming third grooves in the second conductive layer and the absorption layer, thereby defining a photovoltaic cell unit.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: October 22, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen