Patents by Inventor Chun-Li Liu
Chun-Li Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170025403Abstract: In accordance with an embodiment, semiconductor component having a compound semiconductor material based semiconductor device connected to a silicon based semiconductor device and a protection element, wherein the silicon based semiconductor device is a transistor. The protection element is coupled in parallel across the silicon based semiconductor device and may be a resistor, a diode, or a transistor. In accordance with another embodiment, the silicon based semiconductor device is a diode. The compound semiconductor material may be shorted to a source of potential such as, for example, ground, with a shorting element.Type: ApplicationFiled: June 29, 2016Publication date: January 26, 2017Applicant: Semiconductor Components Industries, LLCInventors: Balaji Padmanabhan, Prasad Venkatraman, Chun-Li Liu, Ali Salih
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Publication number: 20170025336Abstract: In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure and a second device receiving structure and a contact extension that is common to the first and second device receiving structures. The first device receiving structure includes a device receiving area and the second device receiving structure includes a drain contact area. A III-N based semiconductor chip has a drain bond pad bonded to the drain contact area and a source bond pad bonded to the contact extension and a gate bond pad bonded to an interconnect. A portion of the silicon based semiconductor chip is bonded to the support device receiving area. In accordance with another embodiment, a method for manufacturing the semiconductor component includes coupling a III-N based semiconductor chip to a portion of the support a silicon based semiconductor chip to another portion of the support.Type: ApplicationFiled: July 6, 2016Publication date: January 26, 2017Applicant: Semiconductor Components Industries, LLCInventors: Balaji Padmanabhan, Prasad Venkatraman, Ali Salih, Mihir Mudholkar, Chun-Li Liu, Jason McDonald
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Publication number: 20170025327Abstract: In accordance with an embodiment, a semiconductor component includes a support having first and second device receiving structures. A semiconductor device configured from a III-N semiconductor material is coupled to the support, wherein the semiconductor device has opposing surfaces. A first bond pad extends from a first portion of the first surface, a second bond pad extends from a second portion of the first surface, and a third bond pad extends from a third portion of the first surface. The first bond pad is coupled to the first device receiving portion, the drain bond pad is coupled to the second device receiving portion, and the third bond pad is coupled to the third lead. In accordance with another embodiment, a method includes coupling a semiconductor chip comprising a III-N semiconductor substrate material to a support.Type: ApplicationFiled: July 8, 2016Publication date: January 26, 2017Applicant: Semiconductor Components Industries, LLCInventors: Balaji Padmanabhan, Ali Salih, Prasad Venkatraman, Chun-Li Liu
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Publication number: 20170025338Abstract: In accordance with an embodiment, a semiconductor component includes a support having first and second device receiving structures. A semiconductor device configured from a III-N semiconductor material is coupled to the support, wherein the semiconductor device has opposing surfaces. A first bond pad extends from a first portion of the first surface, a second bond pad extends from a second portion of the first surface, and a third bond pad extends from a third portion of the first surface. The first bond pad is coupled to the first device receiving portion, the drain bond pad is coupled to the second device receiving portion, and the third bond pad is coupled to the third lead. In accordance with another embodiment, a method includes coupling a semiconductor chip comprising a III-N semiconductor substrate material to a support.Type: ApplicationFiled: July 7, 2016Publication date: January 26, 2017Applicant: Semiconductor Components Industries, LLCInventors: Balaji Padmanabhan, Prasad Venkatraman, Ali Salih, Chun-Li Liu
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Publication number: 20160336313Abstract: An integrated circuit can include a pair of transistors connected in a cascode configuration. In an embodiment, an anode of a diode can be disposed between the gate electrodes of the transistors. In another embodiment, the transistors can include the transistors and a diode, wherein the anode of the diode is coupled to a current electrode of a transistor; and the cathode is coupled to a current electrode of the other transistor. In a particular embodiment, one of the transistors can be an enhancement mode transistor, and the other transistor can be a depletion mode, high mobility electron transistor.Type: ApplicationFiled: May 15, 2015Publication date: November 17, 2016Applicant: Semiconductor Components Industries, LLCInventors: Woochul JEON, Chun-Li LIU
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Publication number: 20160322969Abstract: A half-bridge circuit can include a high-side HEMT, a high-side switch transistor, a low-side HEMT, and a low-side switch transistor. The die substrates of the HEMTs can be coupled to the sources of their corresponding switch transistors. In another aspect, a packaged electronic device for a half-bridge circuit can have a design that can use shorter connectors that help to reduce parasitic inductance and resistance. In a further aspect, a packaged electronic device for a half-bridge circuit can include more than one connection along the bottom of the package allows less lead connections along the periphery of the packaged electronic device and can allow for a smaller package.Type: ApplicationFiled: April 20, 2016Publication date: November 3, 2016Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Balaji PADMANABHAN, Prasad VENKATRAMAN, Peter MOENS, Mihir MUDHOLKAR, Joe FULTON, Philip CELAYA, Stephen ST. GERMAIN, Chun-Li LIU, Jason MCDONALD, Alexander YOUNG, Ali SALIH
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Publication number: 20160322485Abstract: An electronic device can include a bidirectional HEMT. In an aspect, a packaged electronic device can include the bidirectional HEMT can be part of a die having a die substrate connection that is configured to be at a fixed voltage, electrically connected to drain/source or source/drain depending on current flow through the bidirectional HEMT, or electrically float. In another aspect, the electronic device can include Kelvin connections on both the drain/source and source/drain side of the circuit. In a further embodiment, a circuit can include the bidirectional HEMT, switch transistors, and diodes with breakdown voltages to limit voltage swings at the drain/source and source/drain of the switch transistors.Type: ApplicationFiled: April 20, 2016Publication date: November 3, 2016Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Balaji PADMANABHAN, Prasad VENKATRAMAN, Chun-Li LIU, Peter MOENS
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Patent number: 9460995Abstract: In one embodiment, a method of forming a HEMT device may include plating a conductor or a plurality of conductors onto an insulator that overlies a plurality of current carrying electrodes of the HEMT device. The method may also include attaching a connector onto the conductor or attaching a plurality of connectors onto the plurality of conductors.Type: GrantFiled: November 12, 2015Date of Patent: October 4, 2016Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Ali Salih, Chun-Li Liu, Gordon M. Grivna
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Publication number: 20160118490Abstract: In one embodiment, a group III-V transistor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A clamping device is integrated with the group III-V transistor structure and is electrically connected to the first current carrying electrode a third electrode to provide a secondary current path during, for example, an electrical stress event.Type: ApplicationFiled: September 14, 2015Publication date: April 28, 2016Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Balaji PADMANABHAN, Prasad VENKATRAMAN, Zia HOSSAIN, Chun-Li LIU, Jason MCDONALD, Ali SALIH, Alexander YOUNG
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Publication number: 20160118379Abstract: In one embodiment, a cascode rectifier structure includes a group III-V semiconductor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A rectifier device is integrated with the group III-V semiconductor structure and is electrically connected to the first current carrying electrode and to a third electrode. The control electrode is further electrically connected to the semiconductor substrate and the second current path is generally perpendicular to a primary current path between the first and second current carrying electrodes.Type: ApplicationFiled: September 14, 2015Publication date: April 28, 2016Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Balaji PADMANABHAN, Prasad VENKATRAMAN, Zia HOSSAIN, Chun-Li LIU, Woochul JEON, Jason MCDONALD
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Publication number: 20160099314Abstract: In one embodiment, a method of forming an MOS transistor includes forming a threshold voltage (Vth) of the MOS transistor to have a first value at interior portions of the MOS transistor and a second value at other locations within the MOS transistor that are distal from the interior portion wherein the second value is less than the first value.Type: ApplicationFiled: October 7, 2014Publication date: April 7, 2016Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Kirk HUANG, Chun-Li LIU, Ali SALIH
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Publication number: 20160064325Abstract: In one embodiment, a method of forming a HEMT device may include plating a conductor or a plurality of conductors onto an insulator that overlies a plurality of current carrying electrodes of the HEMT device. The method may also include attaching a connector onto the conductor or attaching a plurality of connectors onto the plurality of conductors.Type: ApplicationFiled: November 12, 2015Publication date: March 3, 2016Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Ali SALIH, Chun-Li LIU, Gordon M. GRIVNA
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Publication number: 20160043185Abstract: In accordance with an embodiment, a method for manufacturing a semiconductor component includes providing a semiconductor material having a surface and forming a passivation layer on the semiconductor material Portions of the passivation layer are removed and portions of the semiconductor material exposed by removing the portions of the passivation layer are also removed. A layer of dielectric material is formed on the passivation layer and the exposed portions of the semiconductor material and first and second cavities are formed in the layer of dielectric material. The first cavity exposes a first portion of the semiconductor material and has at least one step shaped sidewall and the second cavity exposes a second portion of the semiconductor material. A first electrode is formed in the first cavity and a second electrode is formed in the second cavity.Type: ApplicationFiled: August 5, 2014Publication date: February 11, 2016Inventor: Chun-Li Liu
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Publication number: 20160043178Abstract: In accordance with an embodiment, a method for manufacturing a semiconductor component includes providing a semiconductor material having a surface, forming an epitaxial layer of carbon doped semiconductor material on the semiconductor substrate, the epitaxial layer having a surface, forming a nucleation layer on the epitaxial layer; and forming a layer of III-nitride material on the nucleation layer. In accordance with another embodiment, the semiconductor component includes a silicon semiconductor substrate of a first conductivity type; a carbon doped epitaxial layer on the silicon semiconductor substrate; a buffer layer over the carbon doped buffer layer; and a channel layer on the buffer layer.Type: ApplicationFiled: August 5, 2014Publication date: February 11, 2016Inventors: Chun-Li Liu, Ali Salih
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Publication number: 20160043218Abstract: In accordance with an embodiment, a method for manufacturing a semiconductor component includes forming a first trench through a plurality of layers of compound semiconductor material. An insulating material is formed on first and second sidewalls of the first trench and first and second sidewalls of the second trench and a trench fill material is formed in the first and second trenches. In accordance with another embodiment, the semiconductor component includes a plurality of layers of compound semiconductor material over a body of semiconductor material and first and second filled trenches extending into the plurality of layers of compound semiconductor material. The first trench has first and second sidewalls and a floor and a first dielectric liner over the first and second sidewalls and the second trench has first and second sidewalls and a floor and second dielectric liner over the first and second sidewalls of the second trench.Type: ApplicationFiled: August 5, 2014Publication date: February 11, 2016Inventors: Peter Moens, Chun-Li Liu
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Publication number: 20160043219Abstract: In accordance with an embodiment, a method for manufacturing a semiconductor component includes forming a first trench through a plurality of layers of compound semiconductor material. An insulating material is formed on first and second sidewalls of the first trench and first and second sidewalls of the second trench and a trench fill material is formed in the first and second trenches. In accordance with another embodiment, the semiconductor component includes a plurality of layers of compound semiconductor material over a body of semiconductor material and first and second filled trenches extending into the plurality of layers of compound semiconductor material. The first trench has first and second sidewalls and a floor and a first dielectric liner over the first and second sidewalls and the second trench has first and second sidewalls and a floor and second dielectric liner over the first and second sidewalls of the second trench.Type: ApplicationFiled: August 5, 2014Publication date: February 11, 2016Inventors: Chun-Li Liu, Balaji Padmanabhan, Ali Salih, Peter Moens
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Publication number: 20160043181Abstract: An electronic device can transistor having a channel layer that includes a compound semiconductor material. In an embodiment, the channel layer overlies a semiconductor layer that includes a carrier barrier region and a carrier accumulation region. The charge barrier region can help to reduce the likelihood that de-trapped carriers from the channel layer will enter the charge barrier region, and the charge accumulation region can help to repel carriers in the channel layer away from the charge barrier layer. In another embodiment, a barrier layer overlies the channel layer. Embodiments described herein may help to produce lower dynamic on-resistance, lower leakage current, another beneficial effect, or any combination thereof.Type: ApplicationFiled: June 17, 2015Publication date: February 11, 2016Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Chun-Li LIU, Ali SALIH
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Patent number: 9257513Abstract: In accordance with an embodiment, a method for manufacturing a semiconductor component includes providing a semiconductor material having a surface and forming a passivation layer on the semiconductor material Portions of the passivation layer are removed and portions of the semiconductor material exposed by removing the portions of the passivation layer are also removed. A layer of dielectric material is formed on the passivation layer and the exposed portions of the semiconductor material and first and second cavities are formed in the layer of dielectric material. The first cavity exposes a first portion of the semiconductor material and has at least one step shaped sidewall and the second cavity exposes a second portion of the semiconductor material. A first electrode is formed in the first cavity and a second electrode is formed in the second cavity.Type: GrantFiled: August 5, 2014Date of Patent: February 9, 2016Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Chun-Li Liu
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Patent number: 9214423Abstract: In one embodiment, a method of forming a HEMT device may include plating a conductor or a plurality of conductors onto an insulator that overlies a plurality of current carrying electrodes of the HEMT device. The method may also include attaching a connector onto the conductor or attaching a plurality of connectors onto the plurality of conductors.Type: GrantFiled: February 6, 2014Date of Patent: December 15, 2015Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Ali Salih, Chun-Li Liu, Gordon M. Grivna
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Patent number: 9123645Abstract: Embodiments include methods of making semiconductor devices with low leakage Schottky contacts. An embodiment includes providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.Type: GrantFiled: November 21, 2013Date of Patent: September 1, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Bruce M. Green, Haldane S. Henry, Chun-Li Liu, Karen E. Moore, Matthias Passlack