Patents by Inventor Chun-Li Liu
Chun-Li Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140264449Abstract: In one embodiment, a HEMT semiconductor device includes an isolation region that may include oxygen wherein the isolation region may extend thorough an ALGaN and GaN layer into an underlying layer.Type: ApplicationFiled: January 23, 2014Publication date: September 18, 2014Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: John Michael Parsey, JR., Chun-Li Liu, Balaji Padmanabhan, Ali Salih
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Publication number: 20140264452Abstract: In one embodiment, a method of forming a HEMT device may include plating a conductor or a plurality of conductors onto an insulator that overlies a plurality of current carrying electrodes of the HEMT device. The method may also include attaching a connector onto the conductor or attaching a plurality of connectors onto the plurality of conductors.Type: ApplicationFiled: February 6, 2014Publication date: September 18, 2014Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Ali Salih, Chun-Li Liu, Gordon M. Grivna
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Publication number: 20140087550Abstract: Embodiments include methods of making semiconductor devices with low leakage Schottky contacts. An embodiment includes providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.Type: ApplicationFiled: November 21, 2013Publication date: March 27, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: BRUCE M. GREEN, HALDANE S. HENRY, CHUN-LI LIU, KAREN E. MOORE, MATTHIAS PASSLACK
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Patent number: 8592878Abstract: Embodiments include semiconductor devices with low leakage Schottky contacts. An embodiment is formed by providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the first mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.Type: GrantFiled: March 8, 2011Date of Patent: November 26, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Bruce M. Green, Haldane S. Henry, Chun-Li Liu, Karen E. Moore, Matthias Passlack
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Publication number: 20110156051Abstract: Embodiments include semiconductor devices with low leakage Schottky contacts. An embodiment is formed by providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the first mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.Type: ApplicationFiled: March 8, 2011Publication date: June 30, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Bruce M. Green, Haldane S. Henry, Chun-Li Liu, Karen E. Moore, Matthias Passlack
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Patent number: 7935620Abstract: Methods and apparatus are described for semiconductor devices. A method comprises providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor, and without removing the first mask, forming a Schottky contact of a first material on the exposed portion of the semiconductor, then removing the first mask, and using a further mask, forming a step-gate conductor of a second material electrically coupled to the Schottky contact and overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.Type: GrantFiled: December 5, 2007Date of Patent: May 3, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Bruce M. Green, Haldane S. Henry, Chun-Li Liu, Karen E. Moore, Matthias Passlack
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Patent number: 7932189Abstract: An electronic device can include a layer of discontinuous storage elements. A dielectric layer overlying the discontinuous storage elements can be substantially hydrogen-free. A process of forming the electronic device can include forming a layer including silicon over the discontinuous storage elements. In one embodiment, the process includes oxidizing at least substantially all of the layer. In another embodiment, the process includes forming the layer using a substantially hydrogen-free silicon precursor material and oxidizing at least substantially all of the layer.Type: GrantFiled: January 26, 2007Date of Patent: April 26, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Tushar P. Merchant, Chun-Li Liu, Ramachandran Muralidhar, Marius K. Orlowski, Rajesh A. Rao, Matthew Stoker
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Patent number: 7928502Abstract: Embodiments of non-volatile semiconductor devices include a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric, and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer.Type: GrantFiled: March 2, 2010Date of Patent: April 19, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Chun-Li Liu, Tushar P. Merchant, Marius K. Orlowski, Matthew W. Stoker
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Patent number: 7821103Abstract: An improved varactor diode (40) is obtained by providing a substrate (41) having a first surface (43), in which are formed a P+ region (53, 46) proximate the first surface (43), a first N region (54, 45) located beneath the P+ region (53, 46), an N well region (56, 44) located beneath the first N region (54, 45) and a first P counter-doped region (55) located between the first N region (54, 45) and the N well region (56, 44), thereby forming an P+NPN structure for the varactor diode. In some embodiments, a second P-type counter-doped region (59) is provided within the N-well region (56, 44) so as to reduce the N doping concentration within the N well region (56, 44) but without creating a further PN junction therein. The net doping profile (52) provides varactor diodes (40) having a larger tuning ratio than varactors (20) without such counter-doped regions. By interchanging N and P regions an N+PNP varactor is obtained.Type: GrantFiled: September 9, 2008Date of Patent: October 26, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Chun-Li Liu, Olin K. Hartin, Jay P. John, Vishal P. Trivedi, James A. Kirchgessner
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Publication number: 20100155825Abstract: Embodiments of non-volatile semiconductor devices include a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric, and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer.Type: ApplicationFiled: March 2, 2010Publication date: June 24, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Chun-Li Liu, Tushar P. Merchant, Marius K. Orlowski, Matthew W. Stoker
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Patent number: 7700438Abstract: Methods and apparatus are provided for non-volatile semiconductor devices. The apparatus comprises a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises, a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can also be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer.Type: GrantFiled: January 30, 2006Date of Patent: April 20, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Chun-Li Liu, Tushar P. Merchant, Marius K. Orlowski, Matthew W. Stoker
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Patent number: 7683443Abstract: An embodiment of a semiconductor device includes a semiconductor substrate having a principal surface, spaced-apart source and drain regions separated by a channel region at the principal surface, and a multilayered gate structure located over the channel region. The multilayered gate structure includes a gate dielectric layer in contact with the channel region, a first conductor comprising a metal oxide overlying the gate dielectric layer, a second conductor overlying the first conductor, and an impurity migration inhibiting layer between the gate dielectric layer and the first conductor or between the first conductor and the second conductor.Type: GrantFiled: December 31, 2008Date of Patent: March 23, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Chun-Li Liu, Marius K. Orlowski, Matthew W. Stoker
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Publication number: 20100059860Abstract: An improved varactor diode (40) is obtained by providing a substrate (41) having a first surface (43), in which are formed a P+ region (53, 46) proximate the first surface (43), a first N region (54, 45) located beneath the P+ region (53, 46), an N well region (56, 44) located beneath the first N region (54, 45) and a first P counter-doped region (55) located between the first N region (54, 45) and the N well region (56, 44), thereby forming an P+NPN structure for the varactor diode. In some embodiments, a second P-type counter-doped region (59) is provided within the N-well region (56, 44) so as to reduce the N doping concentration within the N well region (56, 44) but without creating a further PN junction therein. The net doping profile (52) provides varactor diodes (40) having a larger tuning ratio than varactors (20) without such counter-doped regions. By interchanging N and P regions an N+PNP varactor is obtained.Type: ApplicationFiled: September 9, 2008Publication date: March 11, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Chun-Li Liu, Olin L. Hartin, Jay P. John, James A. Kirchgessner, Vishal P. Trivedi
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Publication number: 20090146191Abstract: Method and apparatus are described for semiconductor devices. The method (100) comprises, providing a partially completed semiconductor device (31-1) including a substrate (21), a semiconductor (22) on the substrate (21) and a passivation layer (25) on the semiconductor (22), and using a first mask (32), locally etching the passivation layer (25) to expose a portion (36) of the semiconductor (22), and without removing the first mask (32) forming a Schottky contact (42-1) of a first material on the exposed portion (36) of the semiconductor (22), then removing the first mask (32) and using a further mask (44), forming a step-gate conductor (48-1) of a second material electrically coupled to the Schottky contact (42-1) and overlying parts (25-1) of the passivation layer (25) adjacent to the Schottky contact (42-1).Type: ApplicationFiled: December 5, 2007Publication date: June 11, 2009Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Bruce M. Green, Haldane S. Henry, Chun-Li Liu, Karen E. Moore, Matthias Passlack
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Patent number: 7544576Abstract: A semiconductor fabrication method includes forming a gate module overlying a substrate. Recesses are etched in the substrate using the gate module as a mask. A barrier layer is deposited over the wafer and anisotropically etched to form barrier “curtains” on sidewalls of the source/drain recesses. A metal layer is deposited wherein the metal layer contacts a semiconductor within the recess. The wafer is annealed to form a silicide selectively. The diffusivity of the metal with respect to the barrier structure material is an order of magnitude less than the diffusivity of the metal with respect to the semiconductor material. The etched recesses may include re-entrant sidewalls. The metal layer may be a nickel layer and the barrier layer may be a titanium nitride layer. Silicon or silicon germanium epitaxial structures may be formed in the recesses overlying the semiconductor substrate.Type: GrantFiled: July 29, 2005Date of Patent: June 9, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Dharmesh Jawarani, Chun-Li Liu, Marius K. Orlowski
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Publication number: 20090115001Abstract: An embodiment of a semiconductor device includes a semiconductor substrate having a principal surface, spaced-apart source and drain regions separated by a channel region at the principal surface, and a multilayered gate structure located over the channel region. The multilayered gate structure includes a gate dielectric layer in contact with the channel region, a first conductor comprising a metal oxide overlying the gate dielectric layer, a second conductor overlying the first conductor, and an impurity migration inhibiting layer between the gate dielectric layer and the first conductor or between the first conductor and the second conductor.Type: ApplicationFiled: December 31, 2008Publication date: May 7, 2009Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Chun-Li Liu, Marius K. Orlowski, Matthew W. Stoker
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Patent number: 7510956Abstract: Methods and apparatus are provided for semiconductor devices. The apparatus comprises a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure located above the channel region. The gate structure comprises, a gate dielectric, preferably of an oxide of Hf, Zr or HfZr substantially in contact with the channel region, a first conductor layer of, for example an oxide of MoSi overlying the gate dielectric, a second conductor layer of, e.g., poly-Si, overlying the first conductor layer and adapted to apply an electrical field to the channel region, and an impurity migration inhibiting layer (e.g., MoSi) located above or below the first conductor layer and adapted to inhibit migration of a mobile impurity, such as oxygen for example, toward the substrate.Type: GrantFiled: January 30, 2006Date of Patent: March 31, 2009Assignee: Fressscale Semiconductor, Inc.Inventors: Chun-Li Liu, Marius K. Orlowski, Matthew W. Stoker
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Publication number: 20080182428Abstract: An electronic device can include a layer of discontinuous storage elements. A dielectric layer overlying the discontinuous storage elements can be substantially hydrogen-free. A process of forming the electronic device can include forming a layer including silicon over the discontinuous storage elements. In one embodiment, the process includes oxidizing at least substantially all of the layer. In another embodiment, the process includes forming the layer using a substantially hydrogen-free silicon precursor material and oxidizing at least substantially all of the layer.Type: ApplicationFiled: January 26, 2007Publication date: July 31, 2008Applicant: Freescale Semiconductor, Inc.Inventors: Tushar P. Merchant, Chun-Li Liu, Ramachandran Muralidhar, Marius K. Orlowski, Rajesh A. Rao, Matthew Stoker
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Publication number: 20070176227Abstract: Methods and apparatus are provided for non-volatile semiconductor devices. The apparatus comprises a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises, a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can also be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer.Type: ApplicationFiled: January 30, 2006Publication date: August 2, 2007Inventors: Chun-Li Liu, Tushar Merchant, Marius Orlowski, Matthew Stoker
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Publication number: 20070176247Abstract: Methods and apparatus are provided for semiconductor devices. The apparatus comprises a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure located above the channel region. The gate structure comprises, a gate dielectric, preferably of an oxide of Hf, Zr or HfZr substantially in contact with the channel region, a first conductor layer of, for example an oxide of MoSi overlying the gate dielectric, a second conductor layer of, e.g., poly-Si, overlying the first conductor layer and adapted to apply an electrical field to the channel region, and an impurity migration inhibiting layer (e.g., MoSi) located above or below the first conductor layer and adapted to inhibit migration of a mobile impurity, such as oxygen for example, toward the substrate.Type: ApplicationFiled: January 30, 2006Publication date: August 2, 2007Inventors: Chun-Li Liu, Marius Orlowski, Matthew Stoker