Patents by Inventor Chun Lu
Chun Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250253275Abstract: A semiconductor device includes a first semiconductor component and a second semiconductor component. The first semiconductor component includes a first substrate, a first dielectric layer and a first pad, wherein the first dielectric layer is disposed over the first substrate and has a first opening, and the first pad is disposed in the first opening. The second semiconductor component includes a second substrate, a second dielectric layer and a second pad, wherein the second dielectric layer is disposed over the second substrate and has a second opening, and the second pad is disposed in the second opening. The first dielectric layer is contact with the second dielectric layer, and the first pad is contact with the second pad.Type: ApplicationFiled: February 6, 2025Publication date: August 7, 2025Applicants: nD-HI Technologies Lab, Inc., ETRON TECHNOLOGY, INC.Inventors: Ho-Ming TONG, Chao-Chun LU
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Patent number: 12381123Abstract: Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.Type: GrantFiled: December 27, 2024Date of Patent: August 5, 2025Assignee: INVENTION AND COLLABORATION LABORATORY, INC.Inventor: Chao-Chun Lu
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Patent number: 12381311Abstract: A multiband printed antenna includes a radiator arranged on an upper portion and one end of a circuit board, and a grounding body. The radiator includes a feed-in part, a first radiation part straightly extended rightward from an upper section of a first right edge of the feed-in part, and a second radiation part sequentially extended rightward, then extended upward, later extended leftward, and further extended downward from a lower section of the first right edge of the feed-in part. The grounding body is arranged on a lower portion of the circuit board. The grounding body is positioned adjacent to a lower portion of a second right edge of the radiator. The grounding body is separated from the radiator.Type: GrantFiled: January 4, 2024Date of Patent: August 5, 2025Assignee: CHENG UEI PRECISION INDUSTRY CO., LTD.Inventors: Lan-Yung Hsiao, Ping-Chun Lu, Shao-Kai Sun
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Patent number: 12368442Abstract: A first clock signal is generated from a reference clock signal. A first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. The first clock signal is propagated towards a first component of an integrated circuit through a clock tree. A second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. The second clock signal is provided to the first component.Type: GrantFiled: November 22, 2023Date of Patent: July 22, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po Chun Lu, Shao-Yu Wang
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Patent number: 12368228Abstract: A wireless dongle includes a circuit board, a universal serial bus connector, a wireless module and a printed antenna. The circuit board has a front edge, a rear edge, a left edge and a right edge. The universal serial bus connector is arranged at a middle of the front edge of the circuit board. The wireless module is arranged at a left area and a middle area of the circuit board. The universal serial bus connector is electrically connected to the wireless module. The wireless module includes a radio frequency chip. The radio frequency chip is arranged on a front right area of the wireless module. The printed antenna is arranged at a right area of the circuit board. The radio frequency chip is arranged between the universal serial bus connector and the printed antenna.Type: GrantFiled: December 14, 2023Date of Patent: July 22, 2025Assignee: CHENG UEI PRECISION INDUSTRY CO., LTD.Inventors: Lan-Yung Hsiao, Ping-Chun Lu, Shao-Kai Sun
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Patent number: 12361998Abstract: This invention discloses sustainable DRAM with principle power supply voltage which is unified with an external logic circuit. The DRAM circuit is configured to couple with the external logic circuit and with a principle power supply voltage source. The DRAM circuit comprises a first sustaining voltage generator and a DRAM core circuit. The first sustaining voltage generator generates a first voltage level which is higher than a voltage level corresponding to a signal ONE utilized in the DRAM circuit. The DRAM core circuit has a DRAM cell comprising an access transistor and a storage capacitor, and the storage capacitor of the DRAM cell is configured to selectively coupled to the first sustaining voltage generator. Wherein, a voltage level of the principle power supply voltage source to the DRAM circuit is the same or substantially the same as that of a principle power supply voltage source to the external logic circuit.Type: GrantFiled: May 28, 2021Date of Patent: July 15, 2025Assignees: Invention And Collaboration Laboratory Pte. Ltd., Etron Technology, Inc.Inventors: Chao-Chun Lu, Bor-Doou Rong, Chun Shiah
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Publication number: 20250219042Abstract: An IC structure includes a memory stack including semiconductor dies horizontally separate with each other, wherein each semiconductor die has a top surface, a bottom surface, four sidewalls, and a plurality of edge pads arranged along a sidewall. The IC structure further includes a memory controller under the first memory stack and electrically connected to the edge pads of each semiconductor die, a processor circuit disposed over and electrically connected to the memory controller, and a packaging substrate under and electrically connected to the memory controller. A die area of the memory controller is larger than the sum of a horizontal cross-section area of the memory stack and a die area of the processor circuit. There is no interposer between the packaging substrate and the memory controller, and there is no TSV in each semiconductor die.Type: ApplicationFiled: February 25, 2025Publication date: July 3, 2025Inventors: HO-MING TONG, CHAO-CHUN LU
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Patent number: 12341076Abstract: Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.Type: GrantFiled: December 13, 2024Date of Patent: June 24, 2025Assignee: INVENTION AND COLLABORATION LABORATORY, INC.Inventor: Chao-Chun Lu
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Patent number: 12341077Abstract: Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.Type: GrantFiled: December 13, 2024Date of Patent: June 24, 2025Assignee: INVENTION AND COLLABORATION LABORATORY, INC.Inventor: Chao-Chun Lu
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Publication number: 20250203838Abstract: A semiconductor cell structure includes a semiconductor substrate with an original semiconductor surface having a first set active regions and a second set of active regions; a STI region surrounding the first set and the second set active regions, a set of PMOS transistors disposed in the first set active regions; a set of NMOS transistors disposed in the second set of active regions; a VDD contacting line electrically coupled to the set of PMOS transistors; a VSS contacting line electrically coupled to the set of NMOS transistors; wherein a bottom surface of each of the source regions and drain regions of the PMOS transistors and the NMOS transistors is isolated from the semiconductor substrate by a localized insulator region, and these localized insulator regions are disposed below the original semiconductor surface.Type: ApplicationFiled: December 3, 2024Publication date: June 19, 2025Applicant: Invention and Collaboration Laboratory, Inc.Inventors: Chao-Chun LU, Juang-Ying CHUEH, Wen-Hsien TU
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Publication number: 20250185280Abstract: A transistor structure includes a semiconductor substrate, a gate structure, a channel region, and a first conductive region. The semiconductor substrate has a semiconductor surface. The gate structure is above the semiconductor surface, and a first concave is formed to reveal the gate structure. The channel region is under the semiconductor surface. The first conductive region is electrically coupled to the channel region, and a second concave is formed to reveal the first conductive region. A mask pattern in a photolithography process is used to define the first concave, and the mask pattern only defines one dimension length of the first concave.Type: ApplicationFiled: February 11, 2025Publication date: June 5, 2025Applicants: Etron Technology, Inc., Invention And Collaboration Laboratory Pte. Ltd.Inventor: Chao-Chun Lu
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Publication number: 20250174539Abstract: A 3D integrated circuit package is provided. The 3D integrated circuit package includes a substrate structure having a first surface and a second surface opposite to the first surface, a high-power die over the substrate structure, a lower-power die over the high-power die, a first interposer between the first surface of the substrate structure and the high-power die, and a second interposer between the high-power die and the lower-power die. The substrate structure includes a thermal enhancement portion located under the high-power die, and at least one of a thermal conductivity or a geometry of the thermal enhancement portion is different from other portions of the substrate structure. A substrate structure of the 3D integrated circuit package is also provided.Type: ApplicationFiled: November 27, 2024Publication date: May 29, 2025Inventors: HO-MING TONG, CHIH-HSUN HSIEH, WEI YEN, CHAO-CHUN LU
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Publication number: 20250161481Abstract: Disclosed are lipid nanoparticle (LNP) delivery systems that specifically target T cells. The LNP delivery system comprises antibodies conjugated to the surface of the LNP, e.g., via maleimide chemistry, that target at least two T cell surface proteins, e.g., CD3 and CD28. The LNP delivery system can have a single population of LNP conjugated to either a bispecific antiCD3/antiCD28 antibody, or two monospecific antiCD3 and antiCD28 antibodies, or two populations of LNP wherein each population comprises a monospecific antibody. The payload of the LNP delivery system can be, e.g., mRNA encoding chimeric antigen receptors (CAR), a linear DNA fragment or a plasmid encoding chimeric antigen receptors (CAR) or therapeutic proteins such as antibodies, components of a gene editing systems (e.g., CRISPR-Cas), small molecules, antibody-drug conjugates (ADC), and any combination thereof, either encapsulated in the LNP or attached to its surface (e.g., conjugated).Type: ApplicationFiled: October 31, 2024Publication date: May 22, 2025Inventors: Yen-Chun LU, Timothy Kosarick EITAS, Nicholas Edward JONES, Leon BROWN, Hao CHEN, Md Munan SHAIK, Ronnie R. WEI, John R. MASCOLA, Elias A. ZERHOUNI, Gary J. NABEL, Zhi-yong YANG, Lan WU, Sian LIAO, Elissa Kathleen LEONARD, Mohui WEI
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Patent number: 12302554Abstract: An IC system includes a package, a plurality of memory dies, and a logic chip. The plurality of memory dies are within the package, each memory die includes a memory region and abridge area, the memory region of each memory die includes a plurality of memory cells and each memory cell includes a first transistor, and the bridge area of each memory die includes a plurality of memory input/output (I/O) pads and a plurality of third transistors. The logic chip includes a logic bridge area and a plurality of second transistors, and the logic bridge area includes a plurality of logic I/O pads. Each memory die is horizontally spaced apart from the logic chip, and the plurality of memory I/O pads of each memory die are electrically coupled to the plurality of logic I/O pads. Each memory die is horizontally spaced apart from each other.Type: GrantFiled: December 5, 2023Date of Patent: May 13, 2025Assignees: Etron Technology, Inc., Invention And Collaboration Laboratory Pte. Ltd.Inventor: Chao-Chun Lu
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Publication number: 20250149375Abstract: A semiconductor device structure includes a semiconductor substrate, an active region, a STI (shallow trench isolation) region, and an interconnection layer. The semiconductor substrate has a semiconductor surface. The active region is within the semiconductor substrate, wherein the active region includes a transistor, and the transistor includes a gate structure with a bottom surface under the semiconductor surface, a first conductive region, and a second conductive region. The STI region surrounds the active region. The interconnection layer is extended beyond the transistor and electrically coupled to the transistor at a connection position under the gate structure. The first conductive region includes a lighted doped region, and a top surface of the lighted doped region is aligned or substantially aligned with an edge of the gate structure.Type: ApplicationFiled: October 30, 2024Publication date: May 8, 2025Applicant: Invention and Collaboration Laboratory, Inc.Inventor: Chao-Chun Lu
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Publication number: 20250140633Abstract: Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.Type: ApplicationFiled: December 27, 2024Publication date: May 1, 2025Applicant: INVENTION AND COLLABORATION LABORATORY, INC.Inventor: Chao-Chun LU
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Patent number: 12280105Abstract: Provided herein is a ribonucleic acid (RNA) encoding a spike (S) protein or an immunogenic fragment thereof of a severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2) comprising at least one non-naturally occurring amino acid mutation. In some embodiments, the S protein is derived from a delta variant. Additionally provided are relevant polynucleotides, vectors, cells, compositions, kits, production methods and methods of use.Type: GrantFiled: February 9, 2024Date of Patent: April 22, 2025Assignee: RNAIMMUNE, INC.Inventors: Neeti Ananthaswamy, Yong-Sik Bong, David Brown, Renxiang Chen, Ju Hyeong Jeon, Zhifeng Long, Dong Shen, Chun Lu, Patrick Y. Lu, Shenggao Tang, Jiaxi He, Ziyang He
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Publication number: 20250125211Abstract: The present invention discloses a device structure including heat removal structure (such as high thermal conductivity column and/or plate within the semiconductor substrate) to enhance heat dissipation. The device structure comprises a semiconductor substrate with an original semiconductor surface; a circuit element located within a semiconductor body region of the semiconductor substrate; and a vertical heat dissipation column in the semiconductor substrate and surrounding the semiconductor body region. Wherein the vertical heat dissipation column comprises a thermal dissipation material with a thermal conductivity higher than that of the semiconductor substrate or that of silicon oxide.Type: ApplicationFiled: December 8, 2023Publication date: April 17, 2025Applicant: Invention and Collaboration Laboratory, Inc.Inventor: Chao-Chun LU
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Publication number: 20250125210Abstract: The present invention discloses a device structure including heat removal structure (such as high thermal conductivity column and/or plate within the semiconductor substrate) to enhance heat dissipation. The device structure comprises a semiconductor substrate with an original semiconductor surface; a circuit element located within a semiconductor body region of the semiconductor substrate; and a horizontal heat dissipation plate in the semiconductor substrate and under the circuit element. Wherein the horizontal heat dissipation plate comprises a first thermal dissipation material with a first thermal conductivity higher than the thermal conductivity of the semiconductor substrate or the thermal conductivity of silicon oxide.Type: ApplicationFiled: December 11, 2023Publication date: April 17, 2025Applicant: Invention and Collaboration Laboratory, Inc.Inventor: Chao-Chun LU
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Publication number: 20250118625Abstract: Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.Type: ApplicationFiled: December 13, 2024Publication date: April 10, 2025Applicant: INVENTION AND COLLABORATION LABORATORY, INC.Inventor: Chao-Chun LU