Patents by Inventor Chun Lu

Chun Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230317693
    Abstract: A die package includes a semiconductor die, a passive component, a molding compound and a redistribution layer (RDL). The semiconductor die includes a first bonding pad. The passive component includes a second bonding pad. The molding compound encloses the semiconductor die and the passive component. The RDL is disposed over the semiconductor die and the passive component and electrically connecting the first bonding pad with the second bonding pad. The semiconductor die is vertically overlapped with the passive component.
    Type: Application
    Filed: September 28, 2022
    Publication date: October 5, 2023
    Applicants: nD-HI Technologies Lab, Inc., ETRON TECHNOLOGY, INC.
    Inventors: Ho-Ming TONG, Chao-Chun LU
  • Publication number: 20230317443
    Abstract: The present invention discloses a method to form a composite semiconductor wafer with a first dimension. The method comprises: attaching a set of thermal dissipation layers to a temporary carrier; bonding the temporary carrier with the set of thermal dissipation layers to a semiconductor substrate with the first dimension, such that the set of thermal dissipation layers are bonded to the semiconductor substrate; and removing the temporary carrier to form composite semiconductor wafer with the first dimension.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 5, 2023
    Applicants: nD-HI Technologies Lab,Inc., ETRON TECHNOLOGY, INC.
    Inventors: Ho-Ming TONG, Wei YEN, Chao-Chun LU
  • Publication number: 20230307682
    Abstract: Provided is an aqueous redox flow battery comprising a positive electrode, a negative electrode, a posolyte chamber containing a posolyte in a solvent, a negolyte chamber containing a polysulfide based negolyte and a soluble organic catalyst in a solvent, and a separator disposed between the posolyte chamber and the negolyte chamber, wherein the soluble organic catalyst has a potential lower than the polysulfide based negolyte.
    Type: Application
    Filed: March 25, 2022
    Publication date: September 28, 2023
    Inventors: Yi-Chun LU, Jiafeng LEI
  • Publication number: 20230307857
    Abstract: An electrical connector with a reinforced tongue has a package, an upper terminal set, a lower terminal set, and a median septum. The package is provided with a tongue. The upper terminal set is mounted in the package and includes multiple upper terminals. The lower terminal set is mounted in the package and includes multiple lower terminals. A median septum is mounted in the package and the tongue, is disposed between the upper terminal set and the lower terminal set, and has a protective wall formed onto two side edges and a front edge of the median septum and longitudinally extends, so as to form two tongue sides and a tongue tip of the tongue. A structural strength of the tongue can be greatly improved, so as to prevent the tongue from being damaged when the electrical connector is plugged or unplugged with improper angle or unsuitable force.
    Type: Application
    Filed: May 2, 2022
    Publication date: September 28, 2023
    Inventors: CHIEN-AN LIAO, CHIEN-CHUN LU, JEN-HAO CHANG
  • Patent number: 11767182
    Abstract: An electric paper tray includes a base, a paper holding element pivotally mounted to at least one side of the base, a power unit arranged at the base, and a lifting module connected between the paper holding element and the power unit. The lifting module is movably mounted under the paper holding element. When the lifting module is driven by the power unit to move to a first position, with respect to the base, the lifting module drives the paper holding element to make the paper holding element rotate to a closed position, when the lifting module is driven by the power unit to move to a second position, with respect to the base, the lifting module drives the paper holding element to make the paper holding element rotate to an opened position.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: September 26, 2023
    Assignee: Foxlink Image Technology Co., Ltd.
    Inventors: Shih Chao Kao, Ching Feng Liao, Jing Hua Fang, Pei Chun Lu
  • Publication number: 20230299069
    Abstract: A standard cell includes plural of transistors including a first type transistor and a second type transistor, plural of contacts coupled to the transistors; at least one input line electrically coupled to the transistors; an output line electrically coupled to the transistors; a VDD contacting line electrically coupled to the transistors; a VSS contacting line electrically coupled to the transistors; wherein the first type transistor includes a first set of fin structures electrically coupled together, the second type transistor includes a second set of fin structures electrically coupled together, and a gap between the first type transistor and the second type transistor is not greater than 3×Fp minus A, wherein Fp is a pitch distance between two adjacent fin structures in the first type transistor and A is a minimum feature size of the standard cell.
    Type: Application
    Filed: September 26, 2022
    Publication date: September 21, 2023
    Applicant: Invention And Collaboration Laboratory Pte. Ltd.
    Inventors: Chao-Chun LU, Li-Ping HUANG, Juang-Ying CHUEH
  • Publication number: 20230290774
    Abstract: The present application discloses a semiconductor device, an electronic system and an electrostatic discharge (ESD) protection method for a semiconductor device thereof. The semiconductor device includes a substrate, an operation solder structure disposed on a first surface of the substrate for receiving an operation signal, a detection solder structure disposed on the first surface of the substrate for receiving a chip connection signal, and a semiconductor chip disposed on a second surface of the substrate. The semiconductor chip includes an operation electrical contact coupled to the operation solder structure, a detection electrical contact coupled to the detection solder structure, an ESD protection unit coupled to the operation electrical contact, and a logic circuit coupled to the detection electrical contact for adjusting capacitance of the ESD protection unit according to the chip connection signal.
    Type: Application
    Filed: May 11, 2023
    Publication date: September 14, 2023
    Inventor: CHUN-LU LEE
  • Patent number: 11756505
    Abstract: Systems, methods, and devices are provided for providing intra-frame luminance scaling to avoid drawing excessive power while still providing exceptional brightness. An instantaneous average pixel luminance of an electronic display may be determined. The instantaneous average pixel luminance may correspond to an amount of light currently being emitted by the electronic display due to a previous image frame and a current image frame. Based at least in part on the instantaneous average pixel luminance, the luminance of a subset of pixels of image data of the current image frame may be adjusted, thereby allowing the electronic display to operate at a relatively high brightness level without exceeding a power limit.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: September 12, 2023
    Assignee: Apple Inc.
    Inventors: Yang Xu, Jie Won Ryu, Kingsuk Brahma, Koorosh Aflatooni, Marc Joseph DeVincentis, Mohammad Ali Jangda, Paolo Sacchetto, Shengkui Gao, Sinan Alousi, Yafei Bi, Chun Lu
  • Publication number: 20230275247
    Abstract: Provided is an aqueous redox flow battery comprising a positive electrode, a negative electrode, a posolyte chamber containing a posolyte, a negolyte chamber containing a polyoxometalate as a negolyte, and a separator disposed between the posolyte chamber and the negolyte chamber, wherein the polyoxometalate has a conductivity of 65 mS cm?1 or more at ?20° C., and the aqueous redox flow battery has a power density of 250 mW cm?2 or more at ?20° C.
    Type: Application
    Filed: February 25, 2022
    Publication date: August 31, 2023
    Inventors: Yi-Chun LU, Fei AI
  • Patent number: 11733790
    Abstract: A ring input device, and more particularly to pressure-sensitive input mechanisms within the ring input device that detect pressure to initiate an operation, is disclosed. Because finger rings are often small and routinely worn, electronic finger rings can be employed as unobtrusive communication devices that are readily available to communicate wirelessly with other devices capable of receiving those communications. Ring input devices according to examples of the disclosure can detect press inputs on its band to generate inputs that can then be wirelessly communicated to companion devices.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: August 22, 2023
    Assignee: Apple Inc.
    Inventors: Michael Beyhs, Richard G. Huizar, Filip Ilievski, Jean Hsiang-Chun Lu, Thayne M. Miller
  • Patent number: 11715706
    Abstract: The present application discloses a semiconductor chip, a semiconductor device and an electrostatic discharge (ESD) protection method for a semiconductor device. The semiconductor chip includes an electrical contact, an application circuit, and an ESD protection unit. The application circuit performs operations according to a one signal received by the electrical contact. The ESD protection unit is coupled to the electrical contact. The capacitance of the ESD protection unit is adjustable.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: August 1, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chun-Lu Lee
  • Publication number: 20230240087
    Abstract: An IC package includes a substrate, a first monolithic die, a second monolithic die and a third monolithic die. A processing unit circuit is formed in the first monolithic die. A plurality of SRAM arrays are formed in the second monolithic die, wherein the plurality of SRAM arrays include at least 5-20 G Bytes. A plurality of DRAM arrays are formed in the third monolithic die, wherein the plurality of DRAM arrays include at least 64-512 G Bytes. The first monolithic die, the second monolithic die and the third monolithic die are vertically stacked above the substrate. The third monolithic die is electrically connected to the first monolithic die through the second monolithic die.
    Type: Application
    Filed: January 20, 2023
    Publication date: July 27, 2023
    Applicant: Invention And Collaboration Laboratory Pte. Ltd.
    Inventor: Chao-Chun LU
  • Publication number: 20230225659
    Abstract: A wearable electronic device includes a housing, and an electrode carrier attached to the housing and having a nonplanar surface. The wearable electronic device includes a set of electrodes, including electrodes positioned at different locations on the nonplanar surface. The wearable electronic device includes a sensor circuit and a switching circuit. The switching circuit is operable to electrically connect a number of different subsets of one or more electrodes in the set of electrodes to the sensor circuit.
    Type: Application
    Filed: January 9, 2023
    Publication date: July 20, 2023
    Inventors: Erdrin Azemi, Ali Moin, Anuranjini Pragada, Jean Hsiang-Chun Lu, Victoria M. Powell, Juri Minxha, Steven P. Hotelling
  • Patent number: 11699900
    Abstract: The present application discloses a semiconductor chip, an electronic device and an electrostatic discharge (ESD) protection method for an electronic device thereof. The semiconductor chip includes an operation electrical contact, a detection electrical contact, an ESD protection unit, and a logic circuit. The operation electrical contact receives an operation signal. The detection electrical contact receives a chip connection signal. The ESD protection unit is coupled to the operation electrical contact. The logic circuit is coupled to the detection electrical contact, and adjusts capacitance of the ESD protection unit according to a chip connection signal received by the detection electrical contact.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: July 11, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chun-Lu Lee
  • Publication number: 20230215416
    Abstract: A biquad hybrid active noise cancellation (ANC) device includes a reference microphone (MIC), an error MiC, a speaker, and a controller. The controller is connected to the reference MiC, the error MiC, and the speaker, wherein the controller includes a feedforward biquad ANC filter, a feedback biquad ANC filter, and a mixer, the feedforward biquad ANC filter processes reference noise to generate a feedforward noise control signal, the feedback biquad ANC filter processes residual noise received by the error MiC to generate a feedback noise control signal, and the feedforward noise control signal generated by the feedforward biquad ANC filter and the feedback noise control signal generated by the feedback biquad ANC filter are added by the mixer and transmits to the speaker for playing.
    Type: Application
    Filed: January 5, 2022
    Publication date: July 6, 2023
    Applicant: BlueX Microelectronics ( Hefei ) Co., Ltd.
    Inventors: Hao-Ming Chen, Yi-Chun Lu, HONGYU LI
  • Publication number: 20230214399
    Abstract: The present invention provides a patent search system, comprising: a database storing a plurality of first patent document data items; and a server accessing the database, the server receiving a first search criterion instruction and then retrieving a plurality of second patent document data items from the plurality of first patent document data items based on the first search criterion instruction, wherein the server receives a first selection instruction associated with a first selected patent document data item in the plurality of second patent document data items, obtains a first patent classification code data item from the first selected patent document data item based on the first selection instruction, and generates a second search criterion instruction based on at least the first search criterion instruction and the first patent classification code data item, the second search criterion instruction including the first patent classification code data item, wherein the server retrieves a plurality of t
    Type: Application
    Filed: June 15, 2022
    Publication date: July 6, 2023
    Applicant: KKLAB TECHNOLOGIES PTE. LTD.
    Inventors: Shih Chun Lu, Shih Hung Lin, Sheng Fu Lin
  • Patent number: 11695003
    Abstract: The present application discloses a semiconductor device, an electronic system and an electrostatic discharge (ESD) protection method for a semiconductor device thereof. The semiconductor device includes a substrate, an operation solder structure disposed on a first surface of the substrate for receiving an operation signal, a detection solder structure disposed on the first surface of the substrate for receiving a chip connection signal, and a semiconductor chip disposed on a second surface of the substrate. The semiconductor chip includes an operation electrical contact coupled to the operation solder structure, a detection electrical contact coupled to the detection solder structure, an ESD protection unit coupled to the operation electrical contact, and a logic circuit coupled to the detection electrical contact for adjusting capacitance of the ESD protection unit according to the chip connection signal.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: July 4, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chun-Lu Lee
  • Publication number: 20230207645
    Abstract: A transistor structure includes a gate, a spacer, a channel region, a first concave, and a first conductive region. The gate is above a silicon surface. The spacer is above the silicon surface and at least covers a sidewall of the gate. The channel region is under the silicon surface. The first conductive region is at least partially formed in the first concave, wherein a conductive region of a neighborhood transistor structure next to the transistor structure is at least partially formed in the first concave.
    Type: Application
    Filed: February 21, 2023
    Publication date: June 29, 2023
    Applicants: Etron Technology, Inc., Invention And Collaboration Laboratory Pte. Ltd.
    Inventors: Chao-Chun Lu, Li-Ping Huang
  • Publication number: 20230202855
    Abstract: The present disclosure discloses a method for strengthening a biological manganese oxidation using a magnetic field and use thereof. The method includes steps of inoculating a manganese-oxidizing microorganism into a culture medium containing Mn2+, performing magnetization treatment in a culture process, and then collecting a biogenic manganese oxide. The method includes steps of performing a primary magnetic field treatment at a magnetic field intensity of 0.2-50 mT for 1-5 h when culturing is performed for 6-12 h, continuing culturing after the primary magnetization treatment, and performing magnetization treatment once every other 24 h for culture time of 72 h. A magnetic field is applied to accelerate an oxidation rate of a manganese-oxidizing microorganism to Mn2+and a biological manganese oxidation rate is respectively improved by 36.4% and 23.8% under an action of an alternating magnetic field or a constant magnetic field within 72 h.
    Type: Application
    Filed: March 6, 2023
    Publication date: June 29, 2023
    Applicant: TONGJI UNIVERSITY
    Inventors: Mei Wang, Zuxin Xu, Bin Dong, Mengke CUI, Sisi Chen, Yifan ZENG, Chun LU
  • Publication number: 20230200040
    Abstract: An integration system includes a first monolithic die and a second monolithic die. The first monolithic die has a processing unit circuit formed therein; and the second monolithic die has a plurality of SRAM arrays formed therein. Wherein the second monolithic die comprises at least 2G Bytes; and the first monolithic die is electrically connected to the second monolithic die.
    Type: Application
    Filed: December 15, 2022
    Publication date: June 22, 2023
    Applicant: Invention And Collaboration Laboratory Pte. Ltd.
    Inventor: Chao-Chun LU