Abstract: The present invention provides a fin structure transistor with precise and well-controlled geometries. Such fin structure transistor comprises a semiconductor substrate with an original surface and an active region formed based on the semiconductor substrate, the active region has a fin structure. A shallow trench isolation region surrounds the active region and a gate structure of the transistor crosses over the fin structure and covers a first portion of the shallow trench isolation region. Wherein the fin structure includes a fin body covered by the gate structure and a fin base portion of which is not covered by the gate structure, and a step-like transition is between the fin body and the fin base.

Abstract: A semiconductor device structure is provided. The semiconductor device has a first dielectric wall between an n-type source/drain region and a p-type source/drain region to physically and electrically isolate the n-type source/drain region and the p-type source/drain region from each other. A second dielectric wall is formed between a first channel region connected to the n-type source/drain region and a second channel region connected to the p-type source/drain region. A contact is formed to physically and electrically connect the n-type source/drain region with the p-type source/drain region, wherein the contact extends over the first dielectric wall. The first electric wall has a gradually decreasing width W5 towards a tip of the dielectric wall from a top contact position between the first dielectric wall and either the n-type source/drain region or the p-type source/drain region.

Abstract: A data collecting system including a component assembled in an electric vehicle, a data collector connected to the component through a bus of the electric vehicle, and a debug server connected to the data collector is disclosed. The component collects different data from the electric vehicle and performs different sending procedures respectively under different situations including: a regular sending-procedure sends regular data to the bus based on a regular frequency; a high-speed sending-procedure starts collecting high-speed data and sending the same to the bus based on a high-speed frequency after a condition is satisfied; and a high-resolution sending-procedure sends high-resolution data to the bus after an error occurs, wherein the high-resolution data is collected within a period of time before and after the error occurs. The data collector collects these data from the bus. The debug server analyzes the data collected by the data collector.

Abstract: A system and methods of forming a dielectric material within a trench are described herein. In an embodiment of the method, the method includes introducing a first precursor into a trench of a dielectric layer, such that portions of the first precursor react with the dielectric layer and attach on sidewalls of the trench. The method further includes partially etching portions of the first precursor on the sidewalls of the trench to expose upper portions of the sidewalls of the trench. The method further includes introducing a second precursor into the trench, such that portions of the second precursor react with the remaining portions of the first precursor to form the dielectric material at the bottom of the trench.

Abstract: A gear module includes a rotating cylinder, a first planetary gear set, a second planetary gear set, a concave-convex structure, and a limit bearing set. The first planetary gear set is accommodated in the rotating cylinder and includes a driven gear; the second planetary gear set includes a positioning frame, second planetary gears pivoted to a positioning frame, a driven gear engaged with the second planetary gears, and the positioning frame has a through hole; the concave-convex structure includes a convex column extended from the rotating cylinder and a concave hole formed on the positioning frame, the convex column is plugged into the concave hole; the limit bearing set includes a first ball bearing sheathing the driven gear and mounted between the driven gear and the through hole, and a second ball bearing sheathing the convex column and mounted between the convex column and the concave hole.

Abstract: A light-emitting device includes: a semiconductor stack, including a first semiconductor layer, an active region and a second semiconductor layer; a first contact electrode and a second contact electrode formed on the semiconductor stack, wherein the first contact electrode includes a first contact part formed on the first semiconductor layer and the second contact electrode includes a second contact part formed on the second semiconductor layer; an insulating stack formed on the semiconductor stack, including an opening on the second contact part; a first electrode pad and a second electrode pad formed on the insulating stack, wherein the second electrode pad filled in the opening and connecting the second contact part; wherein the second electrode pad includes an upper surface, and the upper surface includes a platform area and a depression area on the second contact part; wherein the platform area has a maximum height relative to other areas of the upper surface; wherein an area of a projection of the plat

Abstract: An IC system includes a package, a plurality of memory dies, and a logic chip. The plurality of memory dies are within the package, each memory die includes a memory region and abridge area, the memory region of each memory die includes a plurality of memory cells and each memory cell includes a first transistor, and the bridge area of each memory die includes a plurality of memory input/output (I/O) pads and a plurality of third transistors. The logic chip includes a logic bridge area and a plurality of second transistors, and the logic bridge area includes a plurality of logic I/O pads. Each memory die is horizontally spaced apart from the logic chip, and the plurality of memory I/O pads of each memory die are electrically coupled to the plurality of logic I/O pads. Each memory die is horizontally spaced apart from each other.

Abstract: A transistor structure and a formation method thereof are provided. The transistor structure includes a transistor device, formed on an active region of a semiconductor substrate, and including: a gate structure, disposed on the active region; gate spacers, formed along opposite sidewalls of the gate structure; source/drain structures, formed in recesses of the active region at opposite sides of the gate structure; and buried isolation structures, separately extending along bottom sides of the source/drain structures. Further, a channel portion of the active region between the source/drain structures is strained as a result of a strained etching stop layer lying above or dislocation stressors formed in the source/drain structures.

Abstract: A semiconductor substrate with an original semiconductor surface (OSS); a first gate region; a first concave formed in the semiconductor substrate and below the original semiconductor surface; a curved or depressed shape opening formed along the vertical direction of a sidewall of the semiconductor substrate in the first concave; and a first conductive region formed in the first concave and including a first doping region and a second doping region. Wherein the first doping region is formed based on the curved or depressed shape opening along the vertical direction of the sidewall of the semiconductor substrate.

Abstract: A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming a fin structure over a substrate in a first direction, forming a first gate stack, a second gate stack and a third gate stack across the fin structure, removing the first gate stack to form a trench, depositing a cutting structure in the trench, and forming a first contact plug between the cutting structure and the second gate stack and a second contact plug between the second gate stack and the third gate stack. The fin structure is cut into two segments by the trench. A first dimension of the first contact plug in the first direction is greater than a second dimension of the second contact plug in the first direction.

Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for switching a secondary cell to a primary cell. A user equipment (UE) monitors a first radio condition of the UE for beams of a primary cell and a second radio condition for beams of one or more secondary cells configured for the UE in carrier aggregation. The UE transmits a request to configure a candidate beam of at least one candidate secondary cell as a new primary cell in response to the first radio condition not satisfying a first threshold and the second radio condition for the at least one candidate secondary cell satisfying a second threshold. A base station determines to reconfigure at least one secondary cell as the new primary cell. The base station and the UE perform a handover of the UE to the new primary cell.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes an access transistor defined within an active region of a semiconductor substrate and a storage capacitor disposed on the access transistor. A recessed gate structure of the access transistor extends into the active region from above the active region. Source/drain contacts of the access transistor are disposed on the active region at opposite sides of the recessed gate structure. The storage capacitor includes: a composite bottom electrode, formed by alternately stacked first conductive layers and second conductive layers, wherein each second conductive layer is sandwiched between a pair of the first conductive layers, and tunnels laterally extend through the second conductive layers, respectively; a capacitor dielectric layer, covering inner and outer surfaces of the composite bottom electrode; and a top electrode, in contact with the composite bottom electrode through the capacitor dielectric layer.

Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.

Abstract: A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.

Abstract: A semiconductor structure includes a first gate structure, a second gate structure coupled to the first gate structure, a source region, a first drain region, and a second drain region. The source region is surrounded by the first gate structure and the second gate structure. The first drain region is separated from the source region by the first gate structure. The second drain region is separated from the source region by the second gat structure. A shape of the first drain region and a shape of the second drain region are different from each other from a plan view.

Abstract: A semiconductor device includes a transistor layer, a first via layer over the transistor layer, a first metallization layer over the first via layer, the first metallization layer including first conductors having long axes extending substantially in a first direction, a second via layer over the first metallization layer, and a conductive deep via extending in the second via layer, the first metallization layer, and the first via layer. The first conductors represent a majority of conductive material in the first metallization layer, and a size of the deep via in the first direction in the first metallization layer is substantially less than a minimum length of the first conductors in the first metallization layer.

Abstract: A first clock signal is generated from a reference clock signal. A first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. The first clock signal is propagated towards a first component of an integrated circuit through a clock tree. A second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. The second clock signal is provided to the first component.

Abstract: A memory array circuit includes a semiconductor substrate, a bit line, a complementary bit line, and a bit line sense amplifier circuit. The semiconductor substrate has an original surface. The bit line sense amplifier circuit is connected to the bit line and the complementary bit line, and the bit line sense amplifier circuit includes a first plurality of transistors and a first set of connection lines. Each transistor includes a gate node, a first conductive node, and a second conductive node. The first set of connection lines connects the first plurality of transistors to the bit line and the complementary bit line; wherein the first set of connection lines is above the original surface of the semiconductor substrate, and the bit line and the complementary bit line are under the original surface of the semiconductor substrate.

Abstract: A package component and forming method thereof are provided. The package component includes a substrate and a conductive layer. The substrate includes a first surface. The conductive layer is disposed over the first surface. The conductive layer includes a first conductive feature and a second conductive feature. The second conductive feature covers a portion of the first conductive feature. A resistance of the second conductive feature is lower than a resistance of the first conductive feature.

Abstract: In some embodiments, the present disclosure relates to an integrated chip having an inter-layer dielectric (ILD) structure along a first surface of a substrate having a photodetector. An etch stop layer is over the ILD structure, and a reflector is surrounded by the etch stop layer and the ILD structure. The reflector has a curved surface facing the substrate at a location directly over the photodetector. The curved surface is coupled between a first sidewall and a second sidewall of the reflector. The reflector has larger thicknesses along the first sidewall and the second sidewall than at a center of the reflector between the first sidewall and the second sidewall.