Abstract: A semiconductor package is provided. The semiconductor package includes an integrated circuit (IC) block and a first substrate. The IC block has a first interconnect layer. The first substrate carries the IC block. The first substrate includes a second interconnect layer facing the first interconnect layer and a third interconnect layer opposite to the second interconnect layer. Furthermore, at least one of the second interconnect layer or the third interconnect layer is composed of a dielectric material and a conductive material substantially identical to a corresponding dielectric material and a corresponding conductive material of the first interconnect layer.

Abstract: The present invention discloses a memory cell structure. The memory cell structure includes a silicon substrate, a transistor, and a capacitor. The silicon substrate has a silicon surface. The transistor is coupled to the silicon surface, wherein the transistor includes a gate structure, a first conductive region, and a second conductive region. The capacitor has a storage electrode, wherein the capacitor is over the transistor and the storage electrode is electrically coupled to the second conductive region of the transistor. The capacitor includes a capacitor periphery, and the transistor is located within the capacitor periphery.

Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.

Abstract: A first clock signal is generated from a reference clock signal. A first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. The first clock signal is propagated towards a first component of an integrated circuit through a clock tree. A second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. The second clock signal is provided to the first component.

Abstract: A transistor structure includes a semiconductor substrate, a gate structure, a channel region, and a first conductive region. The semiconductor substrate has a semiconductor surface. The gate structure is above the semiconductor surface, and a first concave is formed to reveal the gate structure. The channel region is under the semiconductor surface. The first conductive region is electrically coupled to the channel region, and a second concave is formed to reveal the first conductive region. A mask pattern in a photolithography process is used to define the first concave, and the mask pattern only defines one dimension length of the first concave.

Abstract: The present disclosure provides a package device. The package device includes a first integrated circuit chip, a second integrated circuit chip, a first input/output pin, and a first electrostatic discharge protection element. The first integrated circuit chip includes a first internal circuit and a first input/output pad disposed on the first integrated circuit chip and coupled to the first internal circuit. The second integrated circuit chip is stacked on the first integrated circuit chip. The second integrated circuit chip includes a second internal circuit and a second input/output pad disposed on the second integrated circuit chip and coupled to the second internal circuit. The first input/output pin is coupled to the first integrated circuit chip and the second integrated circuit chip. The first electrostatic discharge protection element is coupled between the first input/output pad and the first internal circuit.

Abstract: A transistor structure includes a semiconductor substrate, a gate region a spacer, a first trench, a first isolation region and a conductive region. The semiconductor substrate has an active region which has a semiconductor surface. The gate region has a first conductive portion over the semiconductor surface of the semiconductor substrate in the active region and a second conductive portion over the first conductive portion. The spacer covers a sidewall of the gate region. The first trench is formed below the semiconductor surface of the semiconductor substrate in the active region. The first isolation region is in the first trench. The conductive region is positioned on the first isolating region. Wherein a lateral length of the first conductive portion is greater than that of the second conductive portion.

Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) structure includes a semiconductor substrate, a gate structure, a channel region, a channel region, a trench, an isolation region, a first conductive region, and a P-N junction. The semiconductor substrate has a semiconductor surface. The gate structure is above the semiconductor surface. The channel region is under the gate structure. The trench is formed below the semiconductor surface and adjacent to the channel region. The isolation region is in the trench. The first conductive region has a first doping type, and the first conductive region is positioned on the isolating layer and electrically coupled to the channel region. The P-N junction extends upward from the isolation region and along an edge of the first conductive region.

Abstract: The present invention discloses a planar CMOSFET structure used in the peripheral circuit of DRAM chip and in sense amplifiers of array core circuit of DRAM chip, the planar CMOSFET structure comprises a planar P type MOSFET with a first conductive region, a planar N type MOSFET with a second conductive region, and a cross-shape localized isolation region between the planar P type MOSFET and the planar N type MOSFET; wherein the cross-shape localized isolation region includes a horizontally extended isolation region contacts to a bottom side of the first conductive region and a bottom side of the second conductive region.

Abstract: A transistor structure includes a substrate, a source region, a drain region, a trench, and a central pole. The substrate has a convex structure, wherein the convex structure has a conductive channel region. The source region contacts with a first end of the conductive channel region. The drain region contacts with a second end of the conductive channel region. The trench is formed in the convex structure and between the first end and the second end. The central pole is formed in the trench, wherein a material of the central pole is different from that of the conductive channel region.

Abstract: The present invention discloses a memory cell structure. The memory cell structure includes a silicon substrate, a transistor, and a capacitor. The silicon substrate has a silicon surface. The transistor is coupled to the silicon surface, wherein the transistor includes a gate structure, a first conductive region, and a second conductive region. The capacitor has a storage electrode, wherein the capacitor is over the transistor and the storage electrode is electrically coupled to the second conductive region of the transistor. The capacitor includes a capacitor periphery, and the transistor is located within the capacitor periphery.

Abstract: The present disclosure provides a data storage device. The data storage device includes a first area configured to store a first data; a second area configured to store a second data. The second data is associated with the first data, and the first data and/or the second data exclude an ECC.

Abstract: The present disclosure provides a method for controlling a data storage device. The method includes: storing a first data in a first area of a memory of the data storage device; storing a second data in a second area of the memory, wherein the second data is associated with the first; reading the first data and the second data via a first communication interface; and in response to the read first data and second data, generating a first output signal.

Abstract: A ring input device, and more particularly to variable rotational resistance mechanisms within the ring input device that modulate the rotational friction of a rotating outer band to improve the user experience, is disclosed. Because finger rings are often small and routinely worn, electronic finger rings can be employed as unobtrusive communication devices that are readily available to communicate wirelessly with other devices capable of receiving those communications. Ring input devices according to examples of the disclosure can modulate the rotational friction of its rotating outer band in accordance with an item (e.g., user interface or parameter) being manipulated by the band.

Abstract: A semiconductor memory structure includes a plurality of DRAM cells, a bit line, and a sense amplifier. Each DRAM cell includes an access transistor and a storage capacitor. The bit line has a first terminal extended along the plurality of DRAM cells to a second terminal, and the bit line is coupled to each access transistor of the plurality of DRAM cells. The sense amplifier is coupled to the first terminal of the bit line. A capacitance of the bit line per DRAM cell is lower than 20×10?3 fF.

Abstract: An inductor and a power module are respectively provided. The inductor includes an insulating body and a conductive body. The insulating body has a top surface and a bottom surface. The conductive body includes two pin parts and a heat dissipation part. A portion of each of the pin parts is exposed outside the bottom surface. The portions of the two pin parts exposed outside the insulating body are configured to fix to a circuit board. The heat dissipation part is connected to the two pin parts, the heat dissipation part is exposed outside the top surface, and the heat dissipation part is configured to connect to an external heat dissipation member. When the inductor is fixed to the circuit board through the two pin parts exposed outside the bottom surface, the two pin parts and the bottom surface jointly define an accommodating space for accommodating a chip.

Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.

Abstract: The present disclosure provides a method for controlling a data storage device. The method includes: storing a first data in a first area of a memory of the data storage device; storing a second data in a second area of the memory, wherein the second data is associated with the first; reading the first data and the second data via a first communication interface; and in response to the read first data and second data, generating a first output signal.

Abstract: The invention provides novel high-energy density and low-cost flow electrochemical devices incorporating solid-flow electrodes, and further provides methods of using such electrochemical devices. Included are anode and cathode current collector foils that can be made to move during discharge or recharge of the device. Solid-flow devices according to the invention provide improved charging capability due to direct replacement of the conventional electrode stack, higher volumetric and gravimetric energy density, and reduced battery cost due to reduced dimensions of the ion-permeable layer.

Abstract: A high-power seismic wave early warning method is provided to use an earliest-arriving seismic wave to estimate a maximum power value of a later-arriving high-power seismic wave for a target site. When the estimated maximum power value of the later-arriving high-power seismic wave is greater than a warning value, an earthquake early warning is transmitted to an earthquake early warning device that is located at the target site.