Abstract: A system can include a memory device with multiple management units, each management unit made up of multiple blocks, and a processing device, operatively coupled with the memory device, to perform various operations including identifying, among the management units, some complete management units and some incomplete management units, as well as performing one type of operation using one or more complete management units. The operations can also include performing another type of operation using one or more incomplete management units where this other type of operation include writing, to one or more incomplete management units, metadata associated with the data stored in complete management units.

Abstract: Various techniques and schemes pertaining to extremely-high throughput (EHT) multi-link maximum channel switching in wireless communications are described. A station (STA) multi-link device (MLD) receives an indication from a reporting access point (AP) affiliated with an AP MLD on one link of multiple links. The STA MLD determines a channel switching time when a reported AP switches from operating in a current channel of the reported AP to operating in a new channel on one other link of the multiple links based on the indication.

Abstract: The disclosure provides a method for forming an electrostatic discharge (ESD) protection circuit. The method includes providing a circuit comprising a first voltage supply line, an internal circuit, an input/output (I/O) pad coupling to the internal circuit through a line, and a first ESD protection element between the I/O pad and the internal circuit, wherein the first ESD protection element includes a plurality of first ESD units; and forming a first connection circuit on the first ESD protection element, to couple a first group of the first ESD units to the first voltage supply line though a first node and couple the first group of the first ESD units to the line though a second node.

Abstract: A method to process a diamond composite wafer includes the following steps: (a). forming a plurality of through vias in the diamond composite wafer and a first re-distribution layer on a firs side of the diamond composite wafer; (b). attaching a temporary carrier to the first re-distribution layer, and forming a second re-distribution layer on a second side of the diamond composite wafer; and (c). releasing the temporary carrier to form a circuit containing diamond composite wafer.

Abstract: A method to form a first diamond composite wafer, a second diamond composite wafer or a third diamond composite wafer with a predetermined diameter includes the following steps: preparing a plurality of diamond blocks, wherein each diamond block has a dimension smaller than the predetermined diameter; attaching the plurality of diamond blocks to a first semiconductor substrate with the predetermined diameter to form a first temporary composite wafer, wherein a thermal conductivity of the first semiconductor substrate is smaller than that of the diamond block; and filling gaps among the plurality of diamond blocks of the first temporary composite wafer to form the first diamond composite wafer; or attaching the first diamond composite wafer to a second semiconductor substrate with the predetermined diameter to form the second diamond composite wafer, or removing the first semiconductor substrate from the first diamond composite wafer to form the third diamond composite wafer.

Abstract: A semiconductor structure includes a substrate and a first circuit containing composite block over the substrate. The first circuit containing composite block includes a through via therein and a re-distribution layer thereon. The first circuit containing composite block includes a semiconductor block and a diamond block.

Abstract: The memory device includes a substrate, a first ball grid array, a first integrated circuit chip, and a first electrostatic discharge protection element. The first ball grid array is disposed on the substrate. The first integrated circuit chip is disposed on the first ball grid array. The first electrostatic discharge protection element is coupled between the second input/output pad of the first integrated circuit chip and the first internal circuit. The first electrostatic discharge protection element is configured to form a first electrostatic discharge path from the second input/output pad to a first voltage supply line. The first electrostatic discharge protection element includes multiple electrostatic discharge units, and at least one of the electrostatic discharge units is free of coupling between the second input/output pad, the first voltage supply line, and the first internal circuit.

Abstract: Systems and techniques are described herein for processing video data. In some examples, a process is described that can include obtaining a plurality of frames, determining a scene cut in the plurality of frames, and determining a smoothed histogram based on the determined scene cut. For instance, the process can include determining a first characteristic of at least a first frame of the plurality of frames and a second characteristic of at least a second frame of the plurality of frames, determining whether a difference between the first characteristic and the second characteristic is greater than a threshold difference, and determining the scene cut based a determination that the difference between the first characteristic and the second characteristic is greater than the threshold difference.

Abstract: A probe card system is provided. The probe card system, including a tester assembly, a probe head body configured to couple with the tester assembly, a first interconnection structure on a first side of the probe head body, and a probe layer structure on the first interconnection structure on the first side of the probe head body which is configured to engage with a wafer under test (WUT). The probe layer structure includes a sacrificial layer in connection with the first interconnection structure, a bonding layer in connection with the sacrificial layer, and a plurality of probe tips each in connection with respective conductive patterns exposed from the bonding layer and electrically coupled to the first interconnection structure. The sacrificial layer allows removal of the bonding layer and the plurality of probe tips via an etching operation. A method of manufacturing a probe card system is also provided.

Abstract: A semiconductor structure includes a bulk semiconductor substrate with an original semiconductor surface, a semiconductor island region, a shallow trench insulator (STI) region and a buried insulator layer. The semiconductor island region is formed based on the bulk semiconductor substrate. The STI region surrounds the semiconductor island region. The buried insulator layer is a localized insulator layer under the semiconductor island region, wherein a bottom surface of the semiconductor island region is fully isolated from the bulk semiconductor substrate by the buried insulator layer.

Abstract: A memory cell structure includes a silicon substrate, a transistor, and a capacitor. The silicon substrate has a silicon surface. The transistor is coupled to the silicon surface, the transistor includes a gate structure, a first conductive region, and a second conductive region. The capacitor has a signal electrode and a counter electrode, the capacitor is over the transistor, and the signal electrode is electrically coupled to the second conductive region of the transistor and isolated from the first conductive region of the transistor. The counter electrode includes a plurality of sub-electrodes electrically connected with each other.

Abstract: A transistor structure includes a semiconductor substrate, a gate structure, a channel region, and a first conductive region. The semiconductor substrate has a semiconductor surface. The gate structure is above the semiconductor surface, and a first concave is formed to reveal the gate structure. The channel region is under the semiconductor surface. The first conductive region is electrically coupled to the channel region, and a second concave is formed to reveal the first conductive region. A mask pattern in a photolithography process is used to define the first concave, and the mask pattern only defines one dimension length of the first concave.

Abstract: Provided is an aqueous redox flow battery comprising a positive electrode, a negative electrode, a posolyte chamber containing a posolyte, a negolyte chamber containing a polyoxometalate as a negolyte, and a separator disposed between the posolyte chamber and the negolyte chamber, wherein the polyoxometalate has a conductivity of 65 mS cm?1 or more at ?20° C., and the aqueous redox flow battery has a power density of 250 mW cm?2 or more at ?20° C.

Abstract: The present invention provides a new complementary MOSFET structure with localized isolations in silicon substrate to reduce leakages and prevent latch-up. The complementary MOSFET structure comprises a semiconductor wafer substrate with a semiconductor surface, a P type MOSFET comprising a first conductive region, a N type MOSFET comprising a second conductive region, and a cross-shape localized isolation region between the P type MOSFET and the N type MOSFET. Wherein, the cross-shape localized isolation region includes a horizontally extended isolation region below the semiconductor surface, and the horizontally extended isolation region contacts to a bottom side of the first conductive region and a bottom side of the second conductive region.

Abstract: A memory structure includes a semiconductor substrate, an active region, a transistor, and a buried-WL (word line). The semiconductor substrate has an original semiconductor surface. The active region is in the semiconductor substrate and surrounded by a shallow trench isolation (STI) region. The transistor is formed based on the active region. The buried-WL (word line) extends through the active region and the STI region. The buried-WL has variable depth or width along the extension direction of the buried-WL.

Abstract: A semiconductor memory structure includes a semiconductor substrate, a plurality of DRAM (dynamic random access memory) cells, a bit line, a sense amplifier, and a local word line. The semiconductor substrate has a top surface. Each DRAM cell includes an access transistor and a storage capacitor. The bit line has a first terminal extended along the plurality of DRAM cells to a second terminal, and the bit line is coupled to each access transistor of the plurality of DRAM cells. The sense amplifier is coupled to the first terminal of the bit line. The local word line is connected to a gate conductive region of an access transistor of a first DRAM cell in the plurality of DRAM cells. A rising time or a falling time of a voltage signal in the local word line is less than 4 ns.

Abstract: An unified IC system includes a base memory chip, a plurality of stacked memory chips, and a logic chip. The base memory chip includes a memory region and a bridge area, the memory region includes a plurality of memory cells, and the bridge area includes a plurality of memory input/output (I/O) pads and a plurality of third transistors. The plurality of stacked memory chips is positioned above the base memory chip. The logic chip includes a logic bridge area and a plurality of second transistors, the logic bridge includes a plurality of logic I/O pads, wherein the plurality of memory I/O pads are electrically coupled to the plurality of logic I/O pads, and a voltage level of an I/O signal of the third transistor is the same or substantially the same as a voltage level of an I/O signal of the second transistor.

Abstract: A transistor structure includes a semiconductor substrate, a gate region, a first trench, a first isolation region and a first conductive region. The semiconductor substrate is with an original semiconductor surface. The gate region is over the semiconductor surface. The first trench is formed below the original semiconductor surface. The first isolation region is in the first trench. The first conductive region is formed with a first doping region and a second doping region; wherein the first doping region is within the semiconductor substrate and the second doping region is formed outside from the semiconductor substrate.

Abstract: To reduce overall power consumption for an electronic display power management integrated circuit (PMIC), one of multiple electric power converters and/or electric power regulators may be selected based on an electrical load (e.g., due to the total brightness of the content displayed) on the electronic display at a given moment. In some embodiments, the PMIC may include a less efficient heavy load converter designed with high-current handling capability and a more efficient light load (e.g., low current) converter with lower current handling capability. A controller may dynamically select between the converters depending on a present load or an expected load on the electronic display.

Abstract: A transistor structure includes a gate structure, a channel region, a drain region and a source region. The gate structure is positioned above a silicon surface of a first silicon material, the channel region is under the silicon surface, and the channel region includes a first terminal and a second terminal. The drain/source region is independent and not derived from the first silicon material, the drain region includes a first predetermined physical boundary directly connected to the first terminal of the channel region, and the source region includes a second predetermined physical boundary directly connected to the second terminal of the channel region. The drain/source region includes a lower portion below the silicon surface and the bottom of the lower portion of the drain/source region is confined to an isolator, and sidewalls of the drain/source region are confined to spacers except sidewalls of the lower portion of the drain/source region.