Abstract: A semiconductor device structure includes a silicon substrate, a transistor, and an interconnection. The silicon substrate has a silicon surface. The transistor includes a gate structure, a first conductive region, a second conductive region, and a channel under the silicon surface. The interconnection is extended beyond the transistor and coupled to the first conductive region of the transistor. The interconnection is disposed under the silicon surface and isolated from the silicon substrate by an isolation region.

Abstract: A semiconductor device package is provided. The semiconductor device package comprises a first electronic component, a second electronic component above the first electronic component and an interconnection structure disposed external to both the first electronic component and the second electronic component and configured to electrically connect the first electronic component to the second electronic component, a package material configured to hold the first electronic component and the second electronic component together and an external connector configured to electrically connect the first and second electronic components to an external device. The first electronic component has a portion free from being covered by the second electronic component. The external connector is positioned directly above the portion of the first electronic component.

Abstract: A semiconductor package includes: a first semiconductor die disposed over a first substrate; a plurality of second semiconductor dies disposed over the first semiconductor die or adjacent to the first semiconductor die; a plurality of first connectors arranged between and electrically connecting the first semiconductor die and the first substrate; a plurality of second connectors arranged between and electrically connecting two of the second semiconductor dies; a first dielectric layer encapsulating the plurality of second connectors; and a dielectric coating, different from the first dielectric layer, conformally formed on exposed surfaces of the plurality of first connectors and laterally surrounding the first dielectric layer. A plurality of air gaps are arranged between the plurality of first connectors.

Abstract: A semiconductor circuit includes a semiconductor substrate, a transistor, and a voltage source. The semiconductor substrate has an original semiconductor surface. The transistor based on the semiconductor substrate includes a gate structure, a channel region, and a first conductive region. The channel region includes a first terminal and a second terminal. The first conductive region is electrically coupled to the first terminal of the channel region, and the first conductive region includes a top surface and a bottom surface, wherein the bottom surface is below the original semiconductor surface. The voltage source, through the semiconductor substrate, is electrically coupled to the transistor from the bottom surface of the first conductive region.

Abstract: An isoindolinone compound represented by structural formula (I) or a pharmaceutically acceptable salt thereof can be used in the treatment of proliferative diseases. A pharmaceutical composition contains the compound or the salt thereof and a pharmaceutically acceptable carrier.

Abstract: The present invention discloses a semiconductor circuit structure with underground interconnection lines within the semiconductor substrate for signal and power delivery.

Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a first supplying voltage source generating a voltage level corresponding to signal ONE utilized in the DRAM chip, and a DRAM cell which includes an access transistor and a storage capacitor. Wherein a first voltage level is higher than the voltage level corresponding to signal ONE, and the first voltage level is generated by a first sustaining voltage generator. The first sustaining voltage generator is electrically coupled to the storage capacitor of the DRAM cell during a turning-off period of the access transistor of the DRAM cell. A clean up circuit is provided to mitigate the difference between the voltages of BL/BLB and the targeted reference voltage during the equalization period.

Abstract: A wireless dongle includes a circuit board, a universal serial bus connector, a wireless module and a printed antenna. The circuit board has a front edge, a rear edge, a left edge and a right edge. The universal serial bus connector is arranged at a middle of the front edge of the circuit board. The wireless module is arranged at a left area and a middle area of the circuit board. The universal serial bus connector is electrically connected to the wireless module. The wireless module includes a radio frequency chip. The radio frequency chip is arranged on a front right area of the wireless module. The printed antenna is arranged at a right area of the circuit board. The radio frequency chip is arranged between the universal serial bus connector and the printed antenna.

Abstract: A transistor structure includes a gate conductive region, a gate dielectric region, a channel region and a drain region. The gate conductive region is below an original surface of a substrate. The gate dielectric region surrounds the gate conductive region. The channel region surrounds the gate dielectric region. The drain region is horizontally spaced apart from the gate conductive region, wherein the drain region includes a highly doped region; wherein the gate dielectric region includes a first dielectric portion and a second dielectric portion, the first dielectric portion is positioned between the gate conductive region and the highly doped region, and the second dielectric portion is positioned between the gate conductive region and the channel region; wherein a horizontal thickness of the first dielectric portion is greater than that of the second dielectric portion.

Abstract: A high-power seismic wave early warning method is provided to use an earliest-arriving seismic wave to estimate a maximum power value of a later-arriving high-power seismic wave for a target site. When the estimated maximum power value of the later-arriving high-power seismic wave is greater than a warning value, an earthquake early warning is transmitted to an earthquake early warning device that is located at the target site.

Abstract: A multiband printed antenna includes a radiation unit and a grounding unit. The radiation unit is arranged at a right of a circuit board. The radiation unit includes a first radiation part, and a second radiation part which is extended upward and then is bent rightward from a left of a top edge of the first radiation part. The grounding unit is arranged at a left of the circuit board. The grounding unit is separated from the radiation unit. The grounding unit includes a first extension, a second extension straightly extended leftward from a top of a first left edge of the first extension, a grounding part straightly extended leftward from a bottom of the first left edge of the first extension, and a third extension straightly extended leftward from a middle of the first left edge of the first extension.

Abstract: A multiband printed antenna includes a circuit board, a radiator unit and a grounding unit. The radiator unit is arranged on the circuit board. The radiator unit includes a feed-in portion, a first radiant portion slantwise extended upward and rightward from a right of a first top edge of the feed-in portion, and a second radiant portion extended rightward and then extended upward from a first right edge of the feed-in portion. The first radiant portion is formed in a strip shape. The second radiant portion is formed in a lying L shape. A first inner edge of the second radiant portion is separated from a top end of the first radiant portion. The grounding unit is arranged on the circuit board. The radiator unit and the grounding unit are separated from each other.

Abstract: A multiband printed antenna includes a radiator arranged on an upper portion and one end of a circuit board, and a grounding body. The radiator includes a feed-in part, a first radiation part straightly extended rightward from an upper section of a first right edge of the feed-in part, and a second radiation part sequentially extended rightward, then extended upward, later extended leftward, and further extended downward from a lower section of the first right edge of the feed-in part. The grounding body is arranged on a lower portion of the circuit board. The grounding body is positioned adjacent to a lower portion of a second right edge of the radiator. The grounding body is separated from the radiator.

Abstract: A device such as a stylus may have a color sensor. The color sensor may have a color sensing light detector having a plurality of photodetectors each of which measures light for a different respective color channel. The color sensor may also have a light emitter. The light emitter may have an adjustable light spectrum. The light spectrum may be adjusted during color sensing measurements using information such as ambient light color measurements made with a color ambient light sensor that has a plurality of photodetectors each of which measures light for a different respective color channel. An inertial measurement unit may be used to measure the angular orientation between the stylus and an external object during color measurements. Arrangements in which the light emitter is modulated during color sensing may also be used. Measurements from the stylus may be transmitted wirelessly to external equipment.

Abstract: A semiconductor structure includes a ceramic substrate, a first bonding layer, a second bonding layer, a cavity, and a semiconductor layer. The ceramic substrate includes holes on its surface. The first bonding layer is disposed on the surface of the ceramic substrate, and the second bonding layer is bonded to the first bonding layer. The cavity is disposed above the hole and enclosed by the first bonding layer and the second bonding layer. The semiconductor layer extends over the cavity and is disposed along the surface of the second bonding layer.

Abstract: An electrical connector with a reinforced tongue has a package, an upper terminal set, a lower terminal set, and a median septum. The package is provided with a tongue. The upper terminal set is mounted in the package and includes multiple upper terminals. The lower terminal set is mounted in the package and includes multiple lower terminals. A median septum is mounted in the package and the tongue, is disposed between the upper terminal set and the lower terminal set, and has a protective wall formed onto two side edges and a front edge of the median septum and longitudinally extends, so as to form two tongue sides and a tongue tip of the tongue. A structural strength of the tongue can be greatly improved, so as to prevent the tongue from being damaged when the electrical connector is plugged or unplugged with improper angle or unsuitable force.

Abstract: A transistor structure includes a body, a gate structure, a source region, and a drain region. The body has a single convex structure, wherein the convex structure is made of a first semiconductor material, and a trench is formed in the single convex structure. The gate structure has a gate conductive layer and a gate dielectric layer, wherein the gate conductive layer is across over the single convex structure, and a portion of the gate conductive layer is filled in the trench. The source region contacts with a first end of the single convex structure. The drain region contacts with a second end of the single convex structure. A ratio of ON current (Ion) to Off current (Ioff) of the transistor structure is not less than 106.

Abstract: A CMOS circuit includes a bulk semiconductor substrate, a first active region, a PMOS second active region, a (p-type Metal-Oxide-Semiconductor) transistor, a first localized isolating layer, an NMOS (n-type Metal-Oxide-Semiconductor) transistor formed in the second active region, and a second localized isolating layer. The bulk semiconductor substrate has an original semiconductor surface. The first active region and the second active region are formed based on the bulk semiconductor substrate. The PMOS transistor is formed in the first active region. The first localized isolating layer is under the PMOS transistor and at least partially isolates the PMOS transistor from the bulk semiconductor substrate. The NMOS transistor is formed in the second active region. The second localized isolating layer is under the NMOS transistor and at least partially isolates the NMOS transistor from the bulk semiconductor substrate.

Abstract: The memory device includes a substrate, a first ball grid array, a first integrated circuit chip, and a first electrostatic discharge protection element. The first ball grid array is disposed on the substrate. The first integrated circuit chip is disposed on the first ball grid array. The first electrostatic discharge protection element is coupled between the second input/output pad of the first integrated circuit chip and the first internal circuit. The first electrostatic discharge protection element is configured to form a first electrostatic discharge path from the second input/output pad to a first voltage supply line. The first electrostatic discharge protection element includes multiple electrostatic discharge units, and at least one of the electrostatic discharge units is free of coupling between the second input/output pad, the first voltage supply line, and the first internal circuit.

Abstract: The present invention discloses a planar CMOSFET structure used in the peripheral circuit of DRAM chip and in sense amplifiers of array core circuit of DRAM chip, the planar CMOSFET structure comprises a planar P type MOSFET with a first conductive region, a planar N type MOSFET with a second conductive region, and a cross-shape localized isolation region between the planar P type MOSFET and the planar N type MOSFET; wherein the cross-shape localized isolation region includes a horizontally extended isolation region contacts to a bottom side of the first conductive region and a bottom side of the second conductive region. The present invention could be similarly applied to the transistors for CMOS logic circuits as well.