Abstract: A data collecting system including a component assembled in an electric vehicle, a data collector connected to the component through a bus of the electric vehicle, and a debug server connected to the data collector is disclosed. The component collects different data from the electric vehicle and performs different sending procedures respectively under different situations including: a regular sending-procedure sends regular data to the bus based on a regular frequency; a high-speed sending-procedure starts collecting high-speed data and sending the same to the bus based on a high-speed frequency after a condition is satisfied; and a high-resolution sending-procedure sends high-resolution data to the bus after an error occurs, wherein the high-resolution data is collected within a period of time before and after the error occurs. The data collector collects these data from the bus. The debug server analyzes the data collected by the data collector.

Abstract: The disclosure relates to a molecular crowding type electrolyte that comprises at least one type of water-miscible/soluble polymer which acts as molecular crowding agent, a salt and a water. The disclosure also relates to a battery comprising the molecular crowding type electrolyte, and a method of using the molecular crowding electrolyte in electrochemical system such as battery that comprises an anode, a cathode and the molecular crowding type electrolyte.

Abstract: A model building system, a quality prediction system, and a quality management system using the same are provided. The quality management system includes the quality prediction system, a measurement device, and a quality inspection device. The quality prediction system includes the model building system and a model application device. The model building system includes a data transformation device and a model training device. The data transformation device transforms raw measured data, including measurement properties of products, to sets of cluster data and multi-dimensional metadata corresponding to the measurement properties. The model training device creates a prediction model according to the cluster data, the quality inspection results, and the multi-dimensional metadata corresponding to a portion of the products, and then modifies structural parameters of the prediction model according to the raw measured data and the quality inspection results corresponding to the other portion of the products.

Abstract: A first clock signal is generated from a reference clock signal. A first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. The first clock signal is propagated towards a first component of an integrated circuit through a clock tree. A second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. The second clock signal is provided to the first component.

Abstract: A semiconductor device structure includes a silicon substrate, a transistor, and an interconnection. The silicon substrate has a silicon surface. The transistor includes a gate structure, a first conductive region, a second conductive region, and a channel under the silicon surface. The interconnection is extended beyond the transistor and coupled to the first conductive region of the transistor. The interconnection is disposed under the silicon surface and isolated from the silicon substrate by an isolation region.

Abstract: The disclosure is directed to an air purifier and an automobile air conditioner with an air purifier. The air purifier includes a reactor, a column, an air guider and a plurality of light emitting elements. The reactor includes an air inlet and an air outlet. The column is disposed in the reactor, and the column has a N-side walls. The air guider is disposed on the column, and the air guider is coated with a photocatalyst. The light emitting elements are placed on the N side walls of the column configured to irradiate on the photocatalyst, where each of the light emitting elements has an emitting angle of ? and ?*N>360°.

Abstract: A surveillance camera system includes a camera and an image recorder. The image recorder receives a plurality of images captured by the camera and selectively encrypting the plurality of images captured by the camera to generate an encrypted file.

Abstract: A transistor structure includes a semiconductor substrate, a channel layer, a gate structure and a first conductive region. The semiconductor substrate includes a semiconductor surface. The channel layer is independent from the semiconductor substrate and covers the semiconductor surface. The gate structure, covers the channel layer. The first conductive region is coupled to the channel layer.

Abstract: The present invention provides a new complementary MOSFET structure with localized isolations in silicon substrate to reduce leakages and prevent latch-up. The complementary MOSFET structure comprises a semiconductor wafer substrate with a semiconductor surface, a P type MOSFET comprising a first conductive region, a N type MOSFET comprising a second conductive region, and a cross-shape localized isolation region between the P type MOSFET and the N type MOSFET. Wherein, the cross-shape localized isolation region includes a horizontally extended isolation region below the semiconductor surface, and the horizontally extended isolation region contacts to a bottom side of the first conductive region and a bottom side of the second conductive region.

Abstract: The present invention provides a new MOSFET structure with controllable channel length by forming lightly doped drains without using ion implantation. The MOSFET structure comprises a semiconductor wafer substrate with a semiconductor surface, a gate structure over the semiconductor surface, a channel region under the semiconductor surface, and a first conductive region electrically coupled to the channel region. The first conductive region comprises a lightly doped drain region independent from the semiconductor wafer substrate.

Abstract: An unified IC system includes a base memory chip, a plurality of stacked memory chips, and a logic chip. The base memory chip includes a memory region and a bridge area, the memory region includes a plurality of memory cells, and the bridge area includes a plurality of memory input/output (I/O) pads and a plurality of third transistors. The plurality of stacked memory chips is positioned above the base memory chip. The logic chip includes a logic bridge area and a plurality of second transistors, the logic bridge includes a plurality of logic I/O pads, wherein the plurality of memory I/O pads are electrically coupled to the plurality of logic I/O pads, and a voltage level of an I/O signal of the third transistor is the same or substantially the same as a voltage level of an I/O signal of the second transistor.

Abstract: A SRAM cell includes a plurality of transistors, a set of contacts coupled to the plurality of transistors, a word-line electrically coupled to the plurality of transistors, a bit-line and a bit line bar electrically coupled to the plurality of transistors, a VDD contacting line electrically coupled to the plurality of transistors, and a VSS contacting line electrically coupled to the plurality of transistors, wherein as the minimum feature size of the SRAM cell gradually decreases from 28 nm, an area size of the SRAM cell in terms of square of a minimum feature size (?) is the same or substantially the same.

Abstract: The present invention provides a single monolithic the comprising a first schematic circuit manufactured based on a first technology node. A die area of the single monolithic die is smaller than a die area of another monolithic die with a second schematic circuit made based on the first technology node, wherein the first schematic circuit is the same as the second schematic circuit, and the first schematic circuit is a SRAM circuit, a logic circuit, a combination of SRAM and logic circuit, or a major function block circuit.

Abstract: An interconnection structure includes a first dielectric layer, a first conduction layer, a conductor pillar, an upper dielectric layer and an upper conduction layer. The first dielectric layer is disposed over a first terminal of a device. The first conduction layer is disposed over the first dielectric layer. The conductor pillar is connected to the first terminal. The upper dielectric layer is disposed over the first conduction layer. The upper conduction layer is disposed over the upper dielectric layer. The conductor pillar connects to the upper conduction layer but disconnects from the first conduction layer.

Abstract: This invention provides a manufacture method for an interconnection structure including the following steps: forming a first dielectric layer over a first conductive terminal; forming a conductor pillar penetrating through the first dielectric layer, wherein the conductor pillar is electrically connected to the first conductive terminal but not electrically connected to a first conduction layer over the first dielectric layer; forming an upper dielectric layer over the first conduction layer; and forming an upper conduction layer over the upper dielectric layer, wherein the conductor pillar is connected to the upper conduction layer.

Abstract: A scanner includes a scanning module. The scanning module has a scan channel and a scanning glass. A lower surface of the scanner is defined as a bottom wall of the scan channel. The scanning glass is positioned above the scan channel. A bottom surface of the scanning glass is defined as a top wall of the scan channel. The lower surface of the scanner has an upstream turn connected between an upstream section and a middle section of the lower surface of the scanner, the middle section of the lower surface of the scanner is parallel with the bottom surface of the scanning glass.

Abstract: A semiconductor device structure includes a silicon substrate, a transistor, and an interconnection. The silicon substrate has a silicon surface. The transistor includes a gate structure, a first conductive region, a second conductive region, and a channel under the silicon surface. The interconnection is extended beyond the transistor and coupled to the first conductive region of the transistor. The interconnection is disposed under the silicon surface and isolated from the silicon substrate by an isolation region.

Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a first supplying voltage source generating a voltage level corresponding to signal ONE utilized in the DRAM chip, and a DRAM cell which includes an access transistor and a storage capacitor. Wherein a first voltage level is higher than the voltage level corresponding to signal ONE, and the first voltage level is generated by a first sustaining voltage generator. The first sustaining voltage generator is electrically coupled to the storage capacitor of the DRAM cell during a turning-off period of the access transistor of the DRAM cell. A clean up circuit is provided to mitigate the difference between the voltages of BL/BLB and the targeted reference voltage during the equalization period.

Abstract: The present invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word line coupled to a gate terminal of the access transistor. During the period between the word line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.

Abstract: A first clock signal is generated from a reference clock signal. A first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. The first clock signal is propagated towards a first component of an integrated circuit through a clock tree. A second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. The second clock signal is provided to the first component.