Abstract: A SRAM cell structure includes a plurality of transistors, a set of contacts, a word-line, a bit-line, a VDD contacting line and a VSS contacting line. The plurality of transistors include n transistors, wherein n is a positive integral less than 6. The set of contacts are coupled to the plurality of transistors. The word-line is electrically coupled to the plurality of transistors. The bit-line and a bit line bar are electrically coupled to the plurality of transistors. The VDD contacting line is electrically coupled to the plurality of transistors. The VSS contacting line is electrically coupled to the plurality of transistors. Wherein as a minimum feature size of the SRAM cell structure gradually decreases from 28 nm, an area size of the SRAM cell in terms of square of the minimum feature size (?) is the same or substantially the same.

Abstract: A transistor structure includes a gate, a spacer, a channel region, a first concave, and a first conductive region. The gate is above a silicon surface. The spacer is above the silicon surface and at least covers a sidewall of the gate. The channel region is under the silicon surface. The first conductive region is at least partially formed in the first concave, wherein a conductive region of a neighborhood transistor structure next to the transistor structure is at least partially formed in the first concave.

Abstract: A device such as a stylus may have a color sensor. The color sensor may have a color sensing light detector having a plurality of photodetectors each of which measures light for a different respective color channel. The color sensor may also have a light emitter. The light emitter may have an adjustable light spectrum. The light spectrum may be adjusted during color sensing measurements using information such as ambient light color measurements made with a color ambient light sensor that has a plurality of photodetectors each of which measures light for a different respective color channel. An inertial measurement unit may be used to measure the angular orientation between the stylus and an external object during color measurements. Arrangements in which the light emitter is modulated during color sensing may also be used. Measurements from the stylus may be transmitted wirelessly to external equipment.

Abstract: A standard cell includes a plurality of transistors, a set of contacts coupled to the plurality of transistors, at least one input line electrically coupled to the plurality of transistors, an output line electrically coupled to the plurality of transistors, a VDD contacting line electrically coupled to the plurality of transistors and a VSS contacting line electrically coupled to the plurality of transistors. Wherein as a minimum feature size (?) of the standard cell gradually decreases from 22 nm, an area size of the standard cell in terms of ?2 is the same or substantially the same.

Abstract: A semiconductor structure includes a ceramic substrate, a first bonding layer, a second bonding layer, a cavity, and a semiconductor layer. The ceramic substrate includes holes on its surface. The first bonding layer is disposed on the surface of the ceramic substrate, and the second bonding layer is bonded to the first bonding layer. The cavity is disposed above the hole and enclosed by the first bonding layer and the second bonding layer. The semiconductor layer extends over the cavity and is disposed along the surface of the second bonding layer.

Abstract: A transistor structure includes a semiconductor substrate, a gate structure, a channel region, and a first conductive region. The semiconductor substrate has a semiconductor surface. The gate structure is above the semiconductor surface, and a first concave is formed to reveal the gate structure. The channel region is under the semiconductor surface. The first conductive region is electrically coupled to the channel region, and a second concave is formed to reveal the first conductive region. A mask pattern in a photolithography process is used to define the first concave, and the mask pattern only defines one dimension length of the first concave.

Abstract: The present application discloses a semiconductor device, an electronic system and an electrostatic discharge (ESD) protection method for a semiconductor device thereof. The semiconductor device includes a substrate, an operation solder structure disposed on a first surface of the substrate for receiving an operation signal, a detection solder structure disposed on the first surface of the substrate for receiving a chip connection signal, and a semiconductor chip disposed on a second surface of the substrate. The semiconductor chip includes an operation electrical contact coupled to the operation solder structure, a detection electrical contact coupled to the detection solder structure, an ESD protection unit coupled to the operation electrical contact, and a logic circuit coupled to the detection electrical contact for adjusting capacitance of the ESD protection unit according to the chip connection signal.

Abstract: The present application discloses a semiconductor chip, an electronic device and an electrostatic discharge (ESD) protection method for an electronic device thereof. The semiconductor chip includes an operation electrical contact, a detection electrical contact, an ESD protection unit, and a logic circuit. The operation electrical contact receives an operation signal. The detection electrical contact receives a chip connection signal. The ESD protection unit is coupled to the operation electrical contact. The logic circuit is coupled to the detection electrical contact, and adjusts capacitance of the ESD protection unit according to a chip connection signal received by the detection electrical contact.

Abstract: A transistor structure includes a substrate, a gate conductive region, a gate dielectric layer, and a sheet channel layer. The substrate has a body region. The gate conductive region is above the body region. The gate dielectric layer is between the gate conductive region and the body region. The sheet channel layer is disposed between the body region and the gate dielectric layer, wherein the sheet channel layer is independent from the substrate. A doping concentration of the body region is higher than a doping concentration of the sheet channel layer.

Abstract: A transistor structure includes a substrate, a gate conductive region, a gate dielectric layer and a first conductive region. At least a portion of the gate conductive region is disposed below a surface of the substrate. The gate dielectric layer surrounds a bottom wall and sidewalls of the gate conductive region. A bottom wall of the first conductive region is aligned or substantially aligned with a top wall of the gate conductive region.

Abstract: The present application discloses a semiconductor chip, a semiconductor device and an electrostatic discharge (ESD) protection method for a semiconductor device. The semiconductor chip includes an electrical contact, an application circuit, and an ESD protection unit. The application circuit performs operations according to a one signal received by the electrical contact. The ESD protection unit is coupled to the electrical contact. The capacitance of the ESD protection unit is adjustable.

Abstract: A method for forming a transistor structure includes steps as follows: A substrate with an original surface is prepared. Next a gate conductive region is formed, wherein at least a portion of the gate conductive region is disposed below the original surface, and a bottom wall and sidewalls of the gate conductive region is surrounded by a gate dielectric layer. Then, a first conductive region is formed, wherein a bottom wall of the first conductive region is aligned or substantially aligned with a top wall of the gate conductive region.

Abstract: An electrical connector has an upper terminal module, a lower terminal module, and a septum between the upper and the lower terminal modules. The upper terminal module includes an upper block and multiple upper conductive terminals partially covered by the upper block and partially exposed. The lower terminal module includes a lower block and multiple lower conductive terminals partially covered by the lower block and partially exposed. The septum is located between the upper and the lower terminal modules; among them, more than one upper conductive terminal and more than one lower conductive terminal are used for grounding, and are in electrical contact with the septum. The grounding structure design can eliminate resonance to optimize high-frequency characteristics.

Abstract: A flow battery system and methods are provided for eliminating crossover issues of active materials in redox flow batteries. A solid adsorbent with large specific surface area is disposed in an electrolyte of at least one half-cell, in contact with the electrolyte. During a charging process, the active material in a charged state is captured and stored on surfaces of the adsorbent, so that concentrations of the active material in the electrolyte in the charged state is reduced and the crossover is inhibited. During a discharging process, the active material is desorbed from the adsorbent to the electrolyte and pumped into the stack for reaction. The flow battery stack can have a microporous membrane separator. The electrolyte of the flow battery includes zinc iodide as active material and polyethylene glycol (PEG) as an additive.

Abstract: Disclosed is an electrical cell comprising a negative electrode, a positive electrode, and a deposition layer separating the positive electrode and a gas phase that supplies at least one reactive gas; wherein the deposition layer and the positive electrode are in communication with each other via electrolyte(s). Also disclosed is a battery comprising the electrical cell described above and a battery comprising: a cell comprising a negative electrode in communication with an anolyte and a positive electrode in communication with a catholyte; and a gas-liquid reactor, which is fed with the catholyte from the cell and a gas.

Abstract: A device such as a stylus may have a color sensor. The color sensor may have a color sensing light detector having a plurality of photodetectors each of which measures light for a different respective color channel. The color sensor may also have a light emitter. The light emitter may have an adjustable light spectrum. The light spectrum may be adjusted during color sensing measurements using information such as ambient light color measurements made with a color ambient light sensor that has a plurality of photodetectors each of which measures light for a different respective color channel. An inertial measurement unit may be used to measure the angular orientation between the stylus and an external object during color measurements. Arrangements in which the light emitter is modulated during color sensing may also be used. Measurements from the stylus may be transmitted wirelessly to external equipment.

Abstract: A device such as a stylus may have a color sensor. The color sensor may have a color sensing light detector having a plurality of photodetectors each of which measures light for a different respective color channel. The color sensor may also have a light emitter. The light emitter may have an adjustable light spectrum. The light spectrum may be adjusted during color sensing measurements using information such as ambient light color measurements made with a color ambient light sensor that has a plurality of photodetectors each of which measures light for a different respective color channel. An inertial measurement unit may be used to measure the angular orientation between the stylus and an external object during color measurements. Arrangements in which the light emitter is modulated during color sensing may also be used. Measurements from the stylus may be transmitted wirelessly to external equipment.

Abstract: Systems and techniques are described for generating a high dynamic range (HDR) image. An imaging system can be configured to receive a first image captured by an image sensor according to a first exposure time. The imaging system can generate a modified image based on the first image by modifying the first image using a gain setting to simulate a second exposure time based on exposure compensation. The imaging system generates a high dynamic range (HDR) image at least in part by merging multiple images. The multiple images include a second-exposure image that corresponds to the second exposure time. The second-exposure image can be the modified image. The second-exposure image can be based on the modified image, processed variant of the modified image processed for noise reduction based on one or more other images actually captured using the second exposure time.

Abstract: An unified IC system includes a base memory chip, a plurality of stacked memory chips, and a logic chip. The base memory chip includes a memory region and a bridge area, the memory region includes a plurality of memory cells, and the bridge area includes a plurality of memory input/output (I/O) pads and a plurality of third transistors. The plurality of stacked memory chips is positioned above the base memory chip. The logic chip includes a logic bridge area and a plurality of second transistors, the logic bridge includes a plurality of logic I/O pads, wherein the plurality of memory I/O pads are electrically coupled to the plurality of logic I/O pads, and a voltage level of an I/O signal of the third transistor is the same or substantially the same as a voltage level of an I/O signal of the second transistor.

Abstract: A transistor structure includes a gate conductive region, a gate dielectric region, a channel region and a drain region. The gate conductive region is below an original surface of a substrate. The gate dielectric region surrounds the gate conductive region. The channel region surrounds the gate dielectric region. The drain region is horizontally spaced apart from the gate conductive region, wherein the drain region includes a highly doped region; wherein the gate dielectric region includes a first dielectric portion and a second dielectric portion, the first dielectric portion is positioned between the gate conductive region and the highly doped region, and the second dielectric portion is positioned between the gate conductive region and the channel region; wherein a horizontal thickness of the first dielectric portion is greater than that of the second dielectric portion.