Patents by Inventor Chun Yang

Chun Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230320018
    Abstract: A case for receiving at least one electronic device is provided, including a housing, a hinge, a locking member, and a cover. The housing has an accommodating space and an opening communicated with the accommodating space. The hinge is slidably connected to the housing. The cover has an upper side, a lower side, and an outer surface. The lower side is pivotally connected to the hinge. When the locking member affixes the upper side to the housing and the hinge is in a first position relative to the housing, the cover is disposed between an environment space and the accommodating space, and the outer surface faces the environment space. When the locking member is released and the hinge moves to a second position relative to the housing, the cover leaves the position between the environment space and the accommodating space, and the outer surface faces the environment space.
    Type: Application
    Filed: April 1, 2022
    Publication date: October 5, 2023
    Inventors: Shan-Chun YANG, Kuan-Lung WU
  • Patent number: 11778746
    Abstract: An assembly structure of a transformer and a circuit board includes: a circuit board, a packaging chip, a transformer, a first conductive plate, a second conductive plate and a first heat sink. The packaging chip is disposed on the circuit board. The transformer has at least one first output electrode and at least one second output electrode connected to the first output electrode. The first conductive plate is disposed on the transformer and connected to the at least one first output electrode. The second conductive plate is disposed on the transformer and connected to the at least one second output electrode and the circuit board. The first heat sink is connected to the packaging chip and the first conductive plate, is disposed on the circuit board, and is connected to the circuit board and the first conductive plate.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: October 3, 2023
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATION
    Inventors: Tsung-Po Hsu, Yung-Chou Li, Yu-Jen Wei, Chih-Chun Yang
  • Publication number: 20230306144
    Abstract: An electronic device includes a body, a detachable element, a motherboard board and a deformable enclosure. The body includes a first surface and a second surface opposite to each other. The body is formed with a pressure channel. The pressure channel includes a first end and a second end. The pressure channel penetrates the first surface or the second surface. The detachable element covers the first end of the pressure channel. The motherboard is arranged on the body. A sensing element is arranged on the motherboard. The deformable enclosure closes the second end of the pressure channel. When the pressure channel is in a negative pressure state, the deformable enclosure exhibits a first deformation state and does not contact the sensing element. When the pressure channel is not in the negative pressure state, the deformable enclosure exhibits a second deformation state and contacts the sensing element.
    Type: Application
    Filed: February 1, 2023
    Publication date: September 28, 2023
    Inventor: HSUEH-CHUN YANG
  • Publication number: 20230299146
    Abstract: A semiconductor structure includes a nucleation layer disposed on a substrate, an epitaxial growth layer disposed above the nucleation layer, and a superlattice structure disposed between the nucleation layer and the epitaxial growth layer. The superlattice structure includes a plurality of alternately stacked superlattice units, and adjacent two superlattice units include a first superlattice unit and a second superlattice unit. The first superlattice unit includes a first superlattice layer and a second superlattice layer stacked thereon, the second superlattice unit includes a third superlattice layer and a fourth superlattice layer stacked thereon, where each of the first, second, third and fourth superlattice layers includes a plurality of pairs of two sublayers with different compositions from each other.
    Type: Application
    Filed: March 18, 2022
    Publication date: September 21, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chih-Yen Chen, Franky Juanda Lumbantoruan, Chien-Jen Sun, Yi-Wei Lien, Tuan-Wei Wang, Chun-Yang Chen
  • Publication number: 20230299756
    Abstract: A latch circuit includes first and second supply nodes having a first voltage value and a second voltage below the first voltage value, first and second input nodes, first and second output nodes, a first switch coupled between the first and second output nodes and turned on and off responsive to first and second clock signal states, first and second transistors coupled between the respective second and first output nodes and the second supply node. A second switch is coupled between a first transistor gate and the first input node, a third switch is coupled between a second transistor gate and the second input node, and each is turned on and off responsive to the first and second states. During the first state, one of the first or second transistors is part of a low resistance path from the first power supply node to the second power supply node.
    Type: Application
    Filed: May 25, 2023
    Publication date: September 21, 2023
    Inventors: Tsung-Ching (Jim) HUANG, Chan-Hong CHERN, Ming-Chieh HUANG, Chih-Chang LIN, Tien-Chun YANG
  • Publication number: 20230292525
    Abstract: A device structure according to the present disclosure includes a conductive feature disposed in a first dielectric layer, a ferroelectric tunnel junction (FTJ) stack disposed over the conductive feature, a spacer disposed along sidewalls of the FTJ stack, a second dielectric layer disposed over the spacer and the FTJ stack, a second dielectric layer disposed over the spacer and the FTJ stack, and a contact via extending through the second dielectric layer. The FTJ stack includes a bottom electrode layer electrically coupled to the conductive feature, a ferroelectric layer over the bottom electrode layer, and a top electrode layer on the ferroelectric layer. The top electrode layer is formed of a conductive metal oxide.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 14, 2023
    Inventors: Chien Ta Huang, Chia Chi Fan, Chun-Yang Tsai, Kuo-Ching Huang, Harry-Haklay Chuang
  • Publication number: 20230280521
    Abstract: A light source module includes a light guide plate, a light-emitting element, and first and second prism sheets. One of the light-emitting surface and the bottom surface of the light guide plate has strip-shaped microstructures. The bottom surface has bottom microstructures, and the angle between the first surface of each bottom microstructure and the bottom surface is 1° to 17°. The first prism sheet is disposed on the light-emitting surface and between the light-emitting surface and the second prism sheet and includes first prism rods. The second prism sheet includes second prism rods. The aspect ratio of the strip-shaped microstructure is greater than 0.2. The angle between the maximum luminance direction of the light from the light-emitting surface and the normal direction of the light-emitting surface is less than 70°. The light-emitting angle range is less than 40°. A display device including the light source module is also provided.
    Type: Application
    Filed: February 22, 2023
    Publication date: September 7, 2023
    Inventors: TZENG-KE SHIAU, YI-CHENG LIN, CHIA-LIANG KANG, SHIH-WEI LIU, WEI-CHUN YANG, CHENG-YI TSENG
  • Publication number: 20230282260
    Abstract: A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.
    Type: Application
    Filed: March 23, 2022
    Publication date: September 7, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Jian-Jhong Chen, Yi-Ting Wu, Jen-Yu Wang, Cheng-Tung Huang, Po-Chun Yang, Yung-Ching Hsieh
  • Publication number: 20230267090
    Abstract: A charging system includes a source terminal and a sink terminal. The control method of the charging system includes transmitting a bus voltage by the source terminal, determining whether the sink terminal has entered a sink attached state when the sink terminal receives the bus voltage, enabling a message transceiver of the sink terminal if the sink terminal has entered the sink attached state, transmitting a source message to the transceiver of the sink terminal by the source terminal, transmitting a request message to the source terminal by the message transceiver of the sink terminal while the source terminal transmits the source message, and continuing to enable a communication function for communicating with the sink terminal and continuing to transmit the bus voltage to the sink terminal by the source terminal when the source terminal receives the request message.
    Type: Application
    Filed: July 18, 2022
    Publication date: August 24, 2023
    Applicant: RICHTEK TECHNOLOGY CORP.
    Inventors: Tzu-Hsuan Tseng, Tzu-Hsien Chuang, Sheng-Chun Lin, Hao-Chun Yang, Chien-Chih Huang, Heng-Min Chang, Tsung-Jung Wu, Yen-Tung Hung
  • Patent number: 11735436
    Abstract: An apparatus for fabricating a semiconductor device has a housing defining a buffer chamber, a plurality of reactor ports formed in the housing for establishing interfaces with a plurality of process chambers that are to receive a wafer during a fabrication process to fabricate the semiconductor device, a wafer positioning robot positioned within the buffer chamber to transport the wafer between the plurality of process chambers through the plurality of reactor ports, a purge port formed in the housing for introducing a purge gas into the buffer chamber, a pump port formed in the housing for exhausting a portion of the purge gas from the buffer chamber, and a first flow enhancer that directs the purge gas flowing in an axial direction along a longitudinal axis of the purge port into the buffer chamber in a plurality of radial directions relative to the longitudinal axis.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: August 22, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chih-Tsung Lee, Sheng-Chun Yang, Yun-Tzu Chiu, Chao-Hung Wan, Yi-Ming Lin, Chyi-Tsong Ni
  • Publication number: 20230260764
    Abstract: A radio frequency (RF) screen for a microwave powered ultraviolet (UV) lamp system is disclosed. In one example, a disclosed RF screen includes: a sheet comprising a conductive material; and a frame around edges of the sheet. The conductive material defines a predetermined mesh pattern of individual openings across substantially an operative area of the screen. Each of the individual openings has a triangular shape.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 17, 2023
    Inventors: Sheng-chun YANG, Po-Wei LIANG, Chao-Hung WAN, Yi-Ming LIN, Liu Che KANG
  • Publication number: 20230255124
    Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a reactivity reducing coating over one or more lower interconnect layers disposed over a substrate. A bottom electrode layer is formed on and in contact with the reactivity reducing coating. The bottom electrode layer has a first electronegativity that is less than or equal to a second electronegativity of the reactivity reducing coating. A data storage element is formed over the bottom electrode layer and a top electrode layer is formed over the data storage element. The top electrode layer, the data storage element, the reactivity reducing coating, and the bottom electrode layer are patterned to define a memory device.
    Type: Application
    Filed: April 14, 2023
    Publication date: August 10, 2023
    Inventors: Chao-Yang Chen, Chun-Yang Tsai, Kuo-Ching Huang, Wen-Ting Chu, Pili Huang, Cheng-Jun Wu
  • Publication number: 20230254968
    Abstract: Voids are introduced in a copper shape to reduce warpage experienced by a printed circuit board during a reflow process. Copper shapes on an outer layer of a printed circuit board may be used to connect large packages that include ball grid arrays to the printed circuit board. The copper shapes may induce warpage in the printed circuit board during the reflow process. Routing a mesh pattern of voids in the copper shapes may reduce solder ball joint cracking and pad cratering during reflow and make solder joints more reliable. The voids may make the copper shapes less ridged and change the copper heat dissipation profile to remove sharp warpage forces that cause solder joints to experience pad cratering. The voids may be 8 mil x 8 mil cuts or indentations in the copper shape.
    Type: Application
    Filed: May 5, 2021
    Publication date: August 10, 2023
    Inventors: Benito Joseph RODRIGUEZ, Shu-Ming CHANG, Dillip Kumar DASH, Po Chun YANG, Juan-Yi WU
  • Publication number: 20230254180
    Abstract: The present invention relates to a full-electronic turnout security control system for a train-to-train communication and a method thereof. The system comprises: a communication module for realizing an external communication respectively with a resource manager and a maintenance system and an internal communication respectively with a turnout control module, a relay driving module and a relay collection module; the turnout control module for controlling rotation of a turnout and collecting a turnout representation; the relay driving module for driving a relay to turn on or off according to a turnout power source on or off command transmitted by the resource manager; the relay collection module for collecting an on or off state of the collection relay and respectively transmitting the state to the resource manager and the maintenance system through the communication module; and a relay for connecting the relay driving module, the relay collection module and a switch machine driving return line.
    Type: Application
    Filed: September 23, 2021
    Publication date: August 10, 2023
    Inventors: Chun YANG, Jianhua JIANG, Weijuan LI, Qingbiao XU, Cheng ZHANG, Chao LI, Zhenhua HU, Jun WU
  • Patent number: 11719474
    Abstract: A refrigeration cabinet includes a freezing compartment, a first evaporator and a second evaporator. The freezing compartment includes a freezing compartment door, and the first evaporator and the second evaporator are both equipped in the freezing compartment. The first evaporator is turned off and a second evaporator is working while the freezing compartment door is opened.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: August 8, 2023
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Lee-Long Chen, Chun-Yang Hung, Chia-Wei Chen, Yi-Chung Chou
  • Patent number: 11718885
    Abstract: Disclosed is a slag discharging method in a process of producing ultra-low phosphorus steel, which relates to the technical field of iron and steel smelting, and in which molten steel is mixed with lime first to produce basic slag; then converting is performed with oxygen to increase the oxidizability of the basic slag; and a carbon-containing reducing agent is finally added, so that in the process that the carbon is oxidized to release a large amount of carbon monoxide gas, phosphates are captured, and the basic slag is rapidly foamed and overflows from the opening of the steel ladle, so that conditions are no longer available for rephosphorization. Also disclosed is a method for producing ultra-low phosphorus steel, which includes the above-described slag discharging method in a process of producing ultra-low phosphorus steel, and refining and ingotting after slag discharge.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: August 8, 2023
    Assignee: NANYANG HANYE SPECIAL STEEL CO., LTD
    Inventors: Shucheng Zhu, Hu Zhao, Shaopu Xu, Zhongbo Li, Hongyang Li, Yang Yang, Zhenglei Tang, Tao Zhang, Qingbo Liu, Zhanjie Zhang, Jiheng Yuan, Sa Yu, Wenju Kang, Xi Chen, Shuai Zhang, Bo Li, Zhiquan Du, Di Zhao, Liang Li, Peng Jiang, Yansheng Xue, Keyi Fu, Yingjie Wang, Yongqi Yuan, Zhenzhen Dong, Baiming Pang, Haiming Zheng, Liang Chen, Weibo Quan, Xianxing Zhu, Gaojian Yuan, Chun Yang, Yong Wang, Yibo Bai, Gazi Li, Yuliang Lv, Xibin Wang, Yi Ren
  • Publication number: 20230247187
    Abstract: An ocular optical system configured to allow imaging rays from a display image to enter an observer’s eye through the ocular optical system so as to form an image is provided. A direction toward the eye is an eye side, and a direction toward the display image is a display side. The ocular optical system sequentially includes a first and a second lens elements having refracting power from the eye side to the display side along an optical axis. Each lens element includes an eye-side surface and a display-side surface. An optical axis region of the eye-side surface of the first lens element is concave. An optical axis region of the eye-side surface of the second lens element is concave.
    Type: Application
    Filed: January 16, 2023
    Publication date: August 3, 2023
    Applicant: GENIUS ELECTRONIC OPTICAL CO., LTD.
    Inventors: Chun-Yang Huang, Wan-Chun Chen
  • Publication number: 20230233545
    Abstract: Provided herein are methods, uses, and compositions for treating AF in a patient, such as a patient exhibiting heart failure with reduced ejection fraction.
    Type: Application
    Filed: June 14, 2021
    Publication date: July 27, 2023
    Inventors: Jean-Francois TAMBY, Jay M. EDELBERG, Gregory Howard Takeo KURIO, Cynthia Lyle KELLY, Chun YANG, Marcus Patrick HENZE, Carlos L. DEL RIO, Robert Lee ANDERSON, Marius P. SUMANDEA, Jitendra GANJU
  • Patent number: D995212
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: August 15, 2023
    Inventors: Yuanlong Gui, Chun Yang, Bowen Zou
  • Patent number: D995213
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: August 15, 2023
    Inventors: Chun Yang, Zirui Chen