Abstract: An optical substrate having a structured light output surface that comprises rows of laterally arranged snaking, wavy or meandering longitudinal prism structures. The prism structures at the light output surface may be viewed as comprising rows of laterally meandering longitudinal prisms and/or sections of curved segments coupled end-to-end to form the overall meandering longitudinal prism structures. The laterally meandering rows of longitudinal prism structures are arranged in parallel laterally (side-by-side), defining parallel peaks and valleys (a facet is defined between each adjacent peak and valley). In one embodiment, the lateral waviness is regular with a constant or variable wavelength and/or wave amplitude (or extent of lateral deformation). The lateral waviness may generally follow a sinusoidal profile, or other curved profile.

Abstract: A light-emitting device of an embodiment of the present application comprises a semiconductor layer sequence provided with a first main side, a second main side, and an active layer; a beveled trench formed in the semiconductor layer sequence, having a top end close to the second main side, a bottom end, and an inner sidewall connecting the top end and the bottom end. In the embodiment, the inner sidewall is an inclined surface. The light-emitting device further comprises a dielectric layer disposed on the inner sidewall of the beveled trench and the second main side; a first metal layer formed on the dielectric layer; a carrier substrate; and a first connection layer connecting the carrier substrate and the semiconductor layer sequence.

Abstract: A light-emitting diode device, comprising a substrate having a first surface, a plurality of light-emitting units formed on the first surface wherein the plurality of the light emitting units is serially-connected array which comprises a plurality of rows and columns. The plurality of the rows and columns contain at least three light emitting units respectively. The plurality of the light-emitting units in the plurality of light emitting unit rows and light emitting unit columns is connected vertically or horizontally and a plurality of conductive connecting structures contacts the plurality of the light-emitting units wherein at least three light-emitting units in the at least two of the adjacent rows having the same connecting direction and the light-emitting units in at least two of the adjacent light emitting unit rows and the light emitting units in the adjacent row contains one vertical connection and two horizontal connection.

Abstract: A semiconductor device including a substrate, a metal layer, an insulating layer, a semiconductor layer, a drain and a source is provided. The substrate has a surface and a first cavity. The metal layer is disposed on the substrate and covers the surface and inner-wall of the first cavity to define a second cavity corresponding to the first cavity. The insulating layer covers the metal layer and inner-wall of the second cavity to define a third cavity corresponding to the second cavity. The semiconductor layer exposes a portion of the insulating layer and covers the inner-wall of the third cavity to define a fourth cavity corresponding to the third cavity. The drain and source are disposed on the semiconductor layer and covers a portion of the semiconductor layer and a portion of the insulating layer, in which the drain and source expose the fourth cavity.

Abstract: The present invention discloses a structure and method for determining a defect in integrated circuit manufacturing process, wherein the structure comprises a plurality of normal active areas formed in a plurality of first arrays and a plurality of defective active areas formed in a plurality of second arrays. The first arrays and second arrays are interlaced, and the defect is determined by monitoring a voltage contrast from a charged particle microscope image of the active areas.

Abstract: A back contact solar cell includes a solar cell substrate, an intrinsic layer, a second conductive type semiconductor layer and an electrode layer. The solar cell substrate includes a substrate body doped with a first conductive type semiconductor and a plurality of first conductive type semiconductor doped regions. The first conductive type semiconductor doped region is formed on a back side of the substrate body. The intrinsic layer is formed on the back side, and includes a plurality of first openings to expose the first conductive type semiconductor doped regions. The second conductive type semiconductor layer is deposited on the intrinsic layer, and includes a plurality of second openings correspond the first openings. The electrode layer includes a plurality of first electrode regions and a second electrode region. The first electrode regions are disposed on the first conductive type semiconductor doped regions.

Abstract: An organic-inorganic hybrid transistor comprises a flexible substrate, a gate electrode, an organic gate dielectric layer, an oxide semiconductor layer, a first passivation layer, a source electrode and a drain electrode. The gate electrode is disposed on the flexible substrate. The organic gate dielectric layer covers the gate electrode and a portion of the flexible substrate. The oxide semiconductor layer is disposed over the organic gate dielectric layer. The first passivation layer is interposed between and in contact with the oxide semiconductor layer and the organic gate dielectric layer. The source electrode and the drain electrode are respectively connected to different sides of the oxide semiconductor layer.

Abstract: A touch panel includes a substrate, a transparent sensor electrode pattern, a patterned compensation electrode, a passivation layer, a transparent shielding electrode and at least one connection structure. The substrate has a surface and includes a sensor region and a peripheral region. The transparent sensor electrode pattern is disposed on the surface of the substrate and in the sensor region. The patterned compensation electrode is disposed on the surface of the substrate and in the peripheral region, and the patterned compensation electrode and the transparent sensor electrode pattern are electrically isolated. The passivation layer is disposed on the surface of the substrate, covers the transparent sensor electrode pattern, and at least partially exposes the patterned compensation electrode. The transparent shielding electrode is disposed on the passivation layer.

Abstract: A thin film transistor disposed on a substrate is provided. The TFT includes a gate layer, an insulation layer, a carrier transmission layer, a passivation layer, a first source/drain layer, and a second source/drain layer. The gate layer is disposed on the substrate. The insulation layer is disposed on the gate layer. The carrier transmission layer is disposed on the insulation layer. The carrier transmission layer includes an active layer and a mobility enhancement layer. The passivation layer is disposed on the active layer. The first source/drain layer is disposed on the active layer. The second source/drain layer is disposed on the active layer. The mobility enhancement layer includes a first element. The active layer includes a second element. The electronegativity of the first element is smaller than that of the second element to enhance the carrier mobility of the active layer.

Abstract: An electric apparatus including a display and a process unit is provided. The display has an active area and a peripheral area. The display panel including an active device array substrate, an opposite substrate opposite to the active device array substrate and a display medium between the active device array substrate and the opposite substrate. The active device array substrate has a plurality of active devices disposed in the active area and a humidity sensor disposed in the peripheral area. The humidity sensor is a thin film transistor having a metal oxide semiconductor layer. The process unit is electrically connected to the humidity sensor. The process unit calculates a humidity value according to a sensing current from the humidity sensor.

Abstract: A white LED is provided. The white LED includes a P-type layer, a tunneling structure, an N-type layer, an N-type electrode, and a P-type electrode. The tunneling structure is disposed over the P-type layer. The tunneling structure includes a first barrier layer, an active layer and a second barrier layer. The first barrier layer includes a first metal oxide layer. The active layer includes a second metal oxide layer. The second barrier layer includes a third metal oxide layer. The N-type layer is disposed over the tunneling structure. The N-type electrode and the P-type electrode are respectively contacted with the N-type layer and the P-type layer. An energy gap of the second metal oxide layer is lower than an energy gap of the first metal oxide layer and is lower than an energy gap of the third metal oxide layer.

Abstract: A white LED chip includes a P-type layer, a tunneling structure, an N-type layer, an N-type electrode, and a P-type electrode. The tunneling structure is disposed over the P-type layer. The tunneling structure includes a first barrier layer, an active layer and a second barrier layer. The first barrier layer includes a first material layer, the active layer includes a second material layer, and the second barrier layer includes a third material layer. The N-type layer is disposed over the tunneling structure. An energy gap of the second material layer is lower than an energy gap of the first material layer and an energy gap of the third material layer. Each of the first material layer, the second material layer and the third material layer is a metal oxide layer, a metal nitride layer or a metal oxynitride layer.

Abstract: A vertebral fixation apparatus includes a fixation plate respectively secured to the root portions of adjacent transverse processes, rather than the adjacent spinous processes, a superior saddle portion and an inferior saddle portion respectively formed on an upper and a lower portion of the fixation plate for holding a superior spinous process and an inferior spinous process within the superior and inferior saddle portions for stably securing the fixation plate on the adjacent vertebrae for distracting the adjacent vertebrae for relieving the pressure and pain of the spinal cord and nerve.

Abstract: A vertical transistor and a manufacturing method thereof are provided herein. The manufacturing method includes forming a first patterned conductive layer on a substrate; forming a patterned metal oxide layer on the first patterned conductive layer, in which the patterned metal oxide layer includes a first patterned insulator layer, a second patterned insulator layer, and a second patterned conductive layer; forming a semiconductor layer; and forming a third patterned conductive layer. The first patterned insulator layer, the second patterned insulator layer, and the second patterned conductive layer are made by using a single metal oxide material. The oxygen concentration of the second patterned conductive layer is different from the oxygen concentrations of the first patterned insulator layer and the second patterned insulator layer.

Abstract: Virus-like particles (VLPs) of mammalian-hosted viruses, such as SARS-CoV and influenza viruses, have been recombinantly produced from Vero cells. The VLPs closely emulate the exterior of authentic virus particles and are highly immunogenic. They can elicit not only humoral but also cellular immune responses in a mammal. Compositions and methods related to the VLPs are also described.

Abstract: A white LED is provided. The white LED includes a P-type layer, a tunneling structure, an N-type layer, an N-type electrode, and a P-type electrode. The tunneling structure is disposed over the P-type layer. The tunneling structure includes a first barrier layer, an active layer and a second barrier layer. The first barrier layer includes a first metal oxide layer. The active layer includes a second metal oxide layer. The second barrier layer includes a third metal oxide layer. The N-type layer is disposed over the tunneling structure. The N-type electrode and the P-type electrode are respectively contacted with the N-type layer and the P-type layer. An energy gap of the second metal oxide layer is lower than an energy gap of the first metal oxide layer and is lower than an energy gap of the third metal oxide layer.

Abstract: A thin file transistor includes a gate electrode, a source electrode, a drain electrode, a gate-insulating layer, and an oxide semiconductor layer. The oxide semiconductor layer includes indium-gallium-zinc oxide with a formula of InxGayZnzOw, in which x, y and z satisfy the following formulas 1.5?(y/x)?2 and 1.5?(y/z)?2. The gate-insulating layer is positioned between the gate electrode and the oxide semiconductor layer. The source electrode and the drain electrode are respectively connected to two different sides of the oxide semiconductor.

Abstract: A light-emitting device comprises: a first semiconductor layer; a transparent conductive oxide layer including a diffusion region having a first metal material and a non-diffusion region devoid of the first metal material, wherein the non-diffusion region is closer to the first semiconductor layer than the diffusion region; and a metal layer formed on the transparent conductive oxide layer, wherein the metal layer is pervious to a light emitted from the active layer and comprises a pattern.

Abstract: An organic light-emitting display device includes an active array substrate, an encapsulating layer, an organic light-emitting layer, an absorption layer and a sealant. The encapsulating layer is opposite to the active array substrate, and the encapsulating layer has an inner surface facing the active array substrate. The organic light-emitting layer is disposed on the active array substrate. The absorption layer is configured to absorb at least one of moisture and oxygen, and is positioned on the inner surface of the encapsulating layer.