Patents by Inventor Chun-Yuan Wu

Chun-Yuan Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140065775
    Abstract: A method of fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, which includes at least a fin structure and at least a gate semiconductor layer disposed thereon. The gate semiconductor layer covers a portion of the fin structure. Then a sacrificial layer is deposited to cover the fin structure entirely. Subsequently, a top surface of the fin structure is exposed from the sacrificial layer through an etching process. A material layer is then deposited, which covers the gate semiconductor layer, the fin structure and the sacrificial layer conformally. Finally, the material layer is etched until the top surface of the fin structure is exposed and a first spacer is concurrently formed on side surfaces of the gate semiconductor layer.
    Type: Application
    Filed: September 5, 2012
    Publication date: March 6, 2014
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu, Chia-Lin Hsu
  • Patent number: 8664055
    Abstract: A fin field-effect transistor structure includes a substrate, a fin channel and a high-k metal gate. The high-k metal gate is formed on the substrate and the fin channel. A process of manufacturing the fin field-effect transistor structure includes the following steps. Firstly, a polysilicon pseudo gate structure is formed on the substrate and a surface of the fin channel. By using the polysilicon pseudo gate structure as a mask, a source/drain region is formed in the fin channel. After the polysilicon pseudo gate structure is removed, a high-k dielectric layer and a metal gate layer are successively formed. Afterwards, a planarization process is performed on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: March 4, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Teng-Chun Tsai, Chun-Yuan Wu, Chin-Fu Lin, Chih-Chien Liu, Chin-Cheng Chien
  • Patent number: 8647941
    Abstract: A method of forming a semiconductor device includes the following steps. A semiconductor substrate having a first strained silicon layer is provided. Then, an insulating region such as a shallow trench isolation (STI) is formed, where a depth of the insulating region is substantially larger than a depth of the first strained silicon layer. Subsequently, the first strained silicon layer is removed, and a second strained silicon layer is formed to substitute the first strained silicon layer.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: February 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • Patent number: 8647989
    Abstract: The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: February 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Po-Chun Chen
  • Patent number: 8609529
    Abstract: A method of fabricating a through silicon via (TSV) structure, in which, a patterned mask is formed on a substrate, the patterned mask has an opening, a spacer-shaped structure is formed on a sidewall of the opening, and a via hole having a relatively enlarged opening is formed by etching the spacer-shaped structure and the substrate through the opening after the spacer-shaped structure is formed. A TSV structure, in which, a via hole has an opening portion and a body portion, the opening portion is a relatively enlarged opening and has a tapered shape having an opening size of an upper portion greater than an opening size of a lower portion.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: December 17, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Fu Lin, Chun-Yuan Wu, Chih-Chien Liu, Teng-Chun Tsai, Chin-Cheng Chien
  • Publication number: 20130330919
    Abstract: A manufacturing process of an etch stop layer is provided. The manufacturing process includes steps of providing a substrate; forming a gate stack structure over the substrate, wherein the gate stack structure at least comprises a dummy polysilicon layer and a barrier layer; removing the dummy polysilicon layer to define a trench and expose a surface of the barrier layer; forming a repair layer on the surface of the barrier layer and an inner wall of the trench; and forming an etch stop layer on the repair layer. In addition, a manufacturing process of the gate stack structure with the etch stop layer further includes of forming an N-type work function metal layer on the etch stop layer within the trench, and forming a gate layer on the N-type work function metal layer within the trench.
    Type: Application
    Filed: August 7, 2013
    Publication date: December 12, 2013
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Kun-Hsien LIN, Hsin-Fu Huang, Chi-Mao Hsu, Chin-Fu Lin, Chun-Yuan Wu
  • Publication number: 20130288446
    Abstract: A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer.
    Type: Application
    Filed: June 26, 2013
    Publication date: October 31, 2013
    Inventors: Ted Ming-Lang Guo, Chin-Cheng Chien, Shu-Yen Chan, Ling-Chun Chou, Tsung-Hung Chang, Chun-Yuan Wu
  • Publication number: 20130270612
    Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.
    Type: Application
    Filed: April 16, 2012
    Publication date: October 17, 2013
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Chia-Lin Hsu
  • Patent number: 8551847
    Abstract: A method for forming a metal gate is provided. First, a dummy material is formed to completely cover a substrate. Second, a dopant is selectively implanted into the dummy material. Then, some of the dummy material is removed to expose part of the substrate and to form a dummy gate including a dopant region disposed between a first region and a second region. Later an interlayer dielectric layer is formed to surround the dummy gate. Next, a selective etching step is carried out to remove the first region to form a recess without substantially removing the dopant region. Afterwards, the recess is filled with a material set to form a metal gate.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: October 8, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Yuan Wu, Chin-Cheng Chien, Chiu-Hsien Yeh, Yeng-Peng Wang
  • Patent number: 8551829
    Abstract: A method for manufacturing a multi-gate transistor device includes providing a semiconductor substrate having a first patterned semiconductor layer formed thereon, sequentially forming a gate dielectric layer and a gate layer covering a portion of the first patterned semiconductor layer on the semiconductor substrate, removing a portion of the first patterned semiconductor layer to form a second patterned semiconductor layer, and performing a selective epitaxial growth process to form an epitaxial layer on a surface of the second patterned semiconductor layer.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: October 8, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • Publication number: 20130256701
    Abstract: A strained silicon channel semiconductor structure comprises a substrate having an upper surface, a gate structure formed on the upper surface, at least one recess formed in the substrate at lateral sides of the gate structure, wherein the recess has at least one sidewall which has an upper sidewall and a lower sidewall concaved in the direction to the gate structure, and the included angle between the upper sidewall and horizontal plane ranges between 54.5°-90°, and an epitaxial layer filled into the two recesses.
    Type: Application
    Filed: May 30, 2013
    Publication date: October 3, 2013
    Inventors: Chan-Lon Yang, Ted Ming-Lang Guo, Chin-I Liao, Chin-Cheng Chien, Shu-Yen Chan, Chun-Yuan Wu
  • Patent number: 8530980
    Abstract: A gate stack structure with an etch stop layer is provided. The gate stack structure is formed over a substrate. A spacer is formed on a sidewall of the gate stack structure. The gate stack structure includes a gate dielectric layer, a barrier layer, a repair layer and the etch stop layer. The gate dielectric layer is formed on the substrate. The barrier layer is formed on the gate dielectric layer. The barrier layer and an inner sidewall of the spacer collectively define a trench. The repair layer is formed on the barrier layer and an inner wall of the trench. The etch stop layer is formed on the repair layer.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: September 10, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Hsien Lin, Hsin-Fu Huang, Chi-Mao Hsu, Chin-Fu Lin, Chun-Yuan Wu
  • Publication number: 20130228836
    Abstract: A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. Anon-planar semiconductor process is also provided for forming the semiconductor structure.
    Type: Application
    Filed: April 24, 2013
    Publication date: September 5, 2013
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Hung Tsai, Chien-Ting Lin, Chin-Cheng Chien, Chin-Fu Lin, Chih-Chien Liu, Teng-Chun Tsai, Chun-Yuan Wu
  • Publication number: 20130207122
    Abstract: A method for fabricating FinFETs is described. A semiconductor substrate is patterned to form odd fins. Spacers are formed on the substrate and on the sidewalls of the odd fins, wherein each spacer has a substantially vertical sidewall. Even fins are then formed on the substrate between the spacers. A semiconductor structure for forming FinFETs is also described, which is fabricated using the above method.
    Type: Application
    Filed: February 9, 2012
    Publication date: August 15, 2013
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Fu Lin, Chin-Cheng Chien, Chun-Yuan Wu, Teng-Chun Tsai, Chih-Chien Liu
  • Patent number: 8502288
    Abstract: A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: August 6, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Ted Ming-Lang Guo, Chin-Cheng Chien, Shu-Yen Chan, Ling-Chun Chou, Tsung-Hung Chang, Chun-Yuan Wu
  • Publication number: 20130193585
    Abstract: A method of fabricating a through silicon via (TSV) structure, in which, a patterned mask is formed on a substrate, the patterned mask has an opening, a spacer-shaped structure is formed on a sidewall of the opening, and a via hole having a relatively enlarged opening is formed by etching the spacer-shaped structure and the substrate through the opening after the spacer-shaped structure is formed. A TSV structure, in which, a via hole has an opening portion and a body portion, the opening portion is a relatively enlarged opening and has a tapered shape having an opening size of an upper portion greater than an opening size of a lower portion.
    Type: Application
    Filed: February 1, 2012
    Publication date: August 1, 2013
    Inventors: Chin-Fu Lin, Chun-Yuan Wu, Chih-Chien Liu, Teng-Chun Tsai, Chin-Cheng Chien
  • Patent number: 8497198
    Abstract: A semiconductor process is described as follows. A plurality of dummy patterns is formed on a substrate. A mask material layer is conformally formed on the substrate, so as to cover the dummy patterns. The mask material layer has an etching rate different from that of the dummy patterns. A portion of the mask material layer is removed, so as to form a mask layer on respective sidewalls of each dummy pattern. An upper surface of the mask layer and an upper surface of each dummy pattern are substantially coplanar. The dummy patterns are removed. A portion of the substrate is removed using the mask layer as a mask, so as to form a plurality of fin structures and a plurality of trenches alternately arranged in the substrate. The mask layer is removed.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 30, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
  • Patent number: 8476169
    Abstract: A method for fabricating a strained channel semiconductor structure includes providing a substrate, forming at least one gate structure on said substrate, performing an etching process to form two recesses in said substrate at opposites sides of said gate structure, the sidewall of said recess being concaved in the direction to said gate structure and forming an included angle with respect to horizontal plane, and performing a pre-bake process to modify the recess such that said included angle between the sidewall of said recess and the horizontal plane is increased.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: July 2, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chan-Lon Yang, Ted Ming-Lang Guo, Chin-I Liao, Chin-Cheng Chien, Shu-Yen Chan, Chun-Yuan Wu
  • Patent number: 8476164
    Abstract: A method of manufacturing semiconductor device is provided. A substrate at least with a patterned silicon-containing layer on the substrate and spacers adjacent to the patterned silicon-containing layer is provided. A metal layer is formed on the substrate and covers the patterned silicon-containing layer and spacers. Then, a capping layer is formed on the metal layer. A first rapid thermal process is performed to at least make a portion of the metal layer react with the substrate around the spacers to form transitional silicides. The capping layer and the unreacted portions of the metal layer are removed. A first nitride film with a first tensile stress S1 is formed on the substrate. A second rapid thermal process is performed to transfer the transitional silicide to a silicide and transfer the first nitride film to a second nitride film with a second tensile stress S2, wherein S2>S1.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: July 2, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Fu Lin, Chin-Cheng Chien, Chih-Chien Liu, Chia-Lin Hsu, Chun-Yuan Wu
  • Patent number: 8441072
    Abstract: A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. A non-planar semiconductor process is also provided for forming the semiconductor structure.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: May 14, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Shih-Hung Tsai, Chien-Ting Lin, Chin-Cheng Chien, Chin-Fu Lin, Chih-Chien Liu, Teng-Chun Tsai, Chun-Yuan Wu