Abstract: A testing circuit for testing a universal serial bus (USB) of an electronic device includes a controller, a first switch, a pull-down resistor, a gating pull-up resistor, and a second switch. The controller provides a control signal according to a power receiving condition of the electronic device. A control terminal of the first switch is coupled to the controller. The pull-down resistor is coupled between a configuration channel pin of the USB and a first terminal of the first switch. The gating pull-up resistor is coupled between the configuration channel pin and the control terminal of the first switch. A control terminal of the second switch is coupled to the controller. A first terminal of the second switch is coupled to a second terminal of the first switch and a ground pin of the USB. A second terminal of the second switch is coupled to a reference low voltage.

Abstract: A circuit board detection device includes a base, a stage assembly, a first gantry support, and a first probe assembly. The stage assembly is arranged on the base and includes a linear drive module, a rotary motor, and a platform. The platform is configured to carry a circuit board and can be driven by the linear drive module to move along a first axial direction. The platform can also be driven by the rotary motor to rotate relative to a first rotation axis. The first gantry support is fixed on the base and includes a first beam. The first beam extends along a second axial direction perpendicular to the first axial direction to span over the linear drive module, and includes a first probe guide rail. The first probe assembly is arranged on the first probe guide rail to be movable along the second axial direction.

Abstract: A method includes forming a first fin and a second fin over a substrate. The method includes forming a first dummy gate structure that straddles the first fin and the second fin. The first dummy gate structure includes a first dummy gate dielectric and a first dummy gate disposed over the first dummy gate dielectric. The method includes replacing a portion of the first dummy gate with a gate isolation structure. The portion of the first dummy gate is disposed over the second fin. The method includes removing the first dummy gate. The method includes removing a first portion of the first dummy gate dielectric around the first fin, while leaving a second portion of the first dummy gate dielectric around the second fin intact. The method includes forming a gate feature straddling the first fin and the second fin, wherein the gate isolation structure intersects the gate feature.

Abstract: The present disclosure relates an integrated chip. The integrated chip includes an isolation region disposed within a substrate and surrounding an active area. A gate structure is disposed over the substrate and has a base region and a gate extension finger protruding outward from a sidewall of the base region along a first direction to past opposing sides of the active area. A source contact is disposed within the active area and a drain contact is disposed within the active area and is separated from the source contact by the gate extension finger. A first plurality of conductive contacts are arranged on the gate structure and separated along the first direction. The first plurality of conductive contacts are separated by distances overlying the gate extension finger.

Abstract: A controller of a buck-boost conversion circuit and a mode switching method thereof are provided. The controller control operations of multiple switches of the buck-boost conversion circuit to convert an input voltage into an output voltage and provide an output current. The controller includes a slope compensation circuit, a control loop, and a mode switching circuit. The slope compensation circuit generates a slope compensation signal according to a mode switching signal of a current cycle. The control loop is coupled to the slope compensation circuit and the switches respectively, and is configured to generate multiple switch control signals according to the slope compensation signal, a feedback voltage related to the output voltage, and a current sense signal related to the output current to control the operations of the switches respectively. The mode switching circuit is coupled to the slope compensation circuit and the control loop.

Abstract: An optical device package is provided. The optical device package includes a sensor and a light-transmitting region. The sensor includes a sensing region. The light-transmitting region is at least partially in the sensor, and the light-transmitting region allows an external light to transmit therethrough and reach the sensing region. A width of the light-transmitting region adjacent to a level of the sensing region is equal to or smaller than a width of the sensing region.

Abstract: An optical device includes an optical component and an electrical component. The optical component has a sensing surface and a backside surface opposite to the sensing surface. The electrical component is disposed adjacent to the backside surface of the optical component and configured to support the optical component. A portion of the backside surface of the optical component is exposed from the electrical component.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

Abstract: An electrical connector includes: an insulating body; and a first row of terminals and a second row of terminals housed in the insulating body, each terminal in the first row of terminals having a tail portion, a contact portion, and a body portion, the first row of terminals including a signal terminal pair having a pair of signal terminals and a ground terminal arranged on one side of the signal terminal pair, wherein a first center distance between the contact portions of the signal terminal pair is different from a second center distance between the contact portion of the ground terminal and the contact portion of an adjacent signal terminal.

Abstract: An apparatus having a first portion including a first front wall, a first rear wall, and a bottom wall integrally coupled to the first front wall and the first rear wall, and pivotal pin structures integrally coupled to and extending from the first rear wall. The apparatus includes a second portion having a second front wall, a second rear wall, and a top wall integrally coupled to the second front wall and the second rear wall, and pin holders integrally coupled to and extending from the second rear wall and at an offset angle with reference to the top wall. The pivotal pin structure includes a base support connected to the first rear wall and a shaft connected to the base support, and the pin holder defines an opening sized and shaped to accept the shaft. The first and second portions are sized and shaped to be pivotally movable between open and closed configurations.

Abstract: A method for constructing an n-qubit fault tolerant encode for any k-qubit quantum gate M, in any given quantum code [n, k, C], comprising: choosing a number n?k of independent spinors Sr from the first stabilizer C and a first ordered set SC consists of the independent spinors Sr; choosing a number n?k of independent spinors ?r from a second stabilizer ? in the intrinsic coordinate and a second ordered set ?r consists of the independent spinors ?r consist; implementing an encoding Qen, wherein the encoding Qen converts the first ordered set SC to the second ordered set S?, wherein the encoding Qen is a sequential product provided by sequential operations of a number n?k of unitary operators Qr; wherein each of the unitary operator Qr is composed of a single s-rotation or a product of two s-rotations; and wherein the encoding Qen converts and maps the rth independent spinor Sr in the first ordered set SC to the rth independent spinor ?r in the second ordered set S? correspondingly; a fault tolerant action Û i

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a substrate. A resistor overlies the substrate. The resistor comprises a first metal nitride structure, a second metal nitride structure spaced from the first metal nitride structure, and a metal structure disposed between the first metal nitride structure and the second metal nitride structure. A first dielectric structure is disposed over the substrate and the resistor.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

Abstract: A three-dimensional device structure includes a first die including a first semiconductor substrate, a second die disposed on the first die and including a second semiconductor substrate, a dielectric encapsulation (DE) layer disposed on the first die and surrounding the second die, a redistribution layer structure disposed on the second die and the DE layer, and an integrated passive device (IPD) embedded in the DE layer and electrically connected to the first die and the redistribution layer structure.

Abstract: An energy storage apparatus includes a energy storage for storing water and compressed gas; a concrete layer surrounded the energy storage; an inner protection layer arranged on an inner surface of the energy storage.

Abstract: An apparatus having a first portion including a first front wall, a first rear wall, and a bottom wall integrally coupled to the first front wall and the first rear wall, and pivotal pin structures integrally coupled to and extending from the first rear wall. The apparatus includes a second portion having a second front wall, a second rear wall, and a top wall integrally coupled to the second front wall and the second rear wall, and pin holders integrally coupled to and extending from the second rear wall and at an offset angle with reference to the top wall. The pivotal pin structure includes a base support connected to the first rear wall and a shaft connected to the base support, and the pin holder defines an opening sized and shaped to accept the shaft. The first and second portions are sized and shaped to be pivotally movable between open and closed configurations.

Abstract: A three-dimensional device structure includes a die including a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, a through silicon via (TSV) structure that extends through the semiconductor substrate and electrically contacts a metal feature of the interconnect structure, and an integrated passive device (IPD) embedded in the semiconductor substrate and electrically connected to the TSV structure.

Abstract: The invention provides a semiconductor manufacturing method, which comprises providing a substrate with a photoresist layer, forming a hydrophilic film on a surface of the photoresist layer by a spin coating process, and forming a top anti-reflective coating (TARC) on the surface of the hydrophilic film.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a substrate. A resistor overlies the substrate. The resistor comprises a first metal nitride structure, a second metal nitride structure spaced from the first metal nitride structure, and a metal structure disposed between the first metal nitride structure and the second metal nitride structure. A first dielectric structure is disposed over the substrate and the resistor.

Abstract: An electrical connector includes an insulative housing defining a front cavity for receiving and a rear cavity, a terminal assembly assembled in the rear cavity, and a ground member. The terminal assembly includes an upper terminal module, a lower terminal module sandwiching a shielding module therebetween. Said The upper terminal module includes a pair of upper ground terminals. Said The lower terminal module includes a plurality of lower ground terminals. Said The shielding module includes a metallic shielding plate. The ground member is associated with the shielding module to mechanically and electrically connect at least one of the upper ground terminals and the lower ground terminals with the shielding plate.