Patents by Inventor Chung Tsai

Chung Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240162109
    Abstract: In an embodiment, a package includes an integrated circuit device attached to a substrate; an encapsulant disposed over the substrate and laterally around the integrated circuit device, wherein a top surface of the encapsulant is coplanar with the top surface of the integrated circuit device; and a heat dissipation structure disposed over the integrated circuit device and the encapsulant, wherein the heat dissipation structure includes a spreading layer disposed over the encapsulant and the integrated circuit device, wherein the spreading layer includes a plurality of islands, wherein at least a portion of the islands are arranged as lines extending in a first direction in a plan view; a plurality of pillars disposed over the islands of the spreading layer; and nanostructures disposed over the pillars.
    Type: Application
    Filed: January 10, 2023
    Publication date: May 16, 2024
    Inventors: Hung-Yi Kuo, Chen-Hua Yu, Kuo-Chung Yee, Yu-Jen Lien, Ke-Han Shen, Wei-Kong Sheng, Chung-Shi Liu, Szu-Wei Lu, Tsung-Fu Tsai, Chung-Ju Lee, Chih-Ming Ke
  • Publication number: 20240157217
    Abstract: A golf teaching method and a golf teaching system are provided. The golf teaching method includes: configuring image capturing devices and golf simulator to capture swing images and corresponding simulator data records, when a user performs a golf swing; configuring an expert model that includes expert motion information and corresponding correction suggestion information; configuring a computing device to perform an analysis process on the swing images and the simulator data records to divide the golf swing into user motions according to stages and obtaining records of user motion information corresponding to the plurality of stages, and to compare the user motion information with the corresponding expert motion information in each stage through the expert model, and to provide the corresponding correction suggestion information according to a comparison result; and configuring a user interface to provide the correction suggestion information.
    Type: Application
    Filed: April 20, 2023
    Publication date: May 16, 2024
    Inventors: CHENG-HUNG TSAI, CHIA-YU JIH, CHIH-CHUNG CHIEN, LI-LIN LU, SHAO-JUN TAN, WEN-FU LAI
  • Publication number: 20240153943
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 9, 2024
    Inventors: Sheng-Fu Hsu, Ta-Yuan Kung, Chen-Liang Chu, Chih-Chung Tsai
  • Publication number: 20240145554
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.
    Type: Application
    Filed: January 11, 2024
    Publication date: May 2, 2024
    Inventors: Yao-Chung Chang, Chun Lin Tsai, Ru-Yi Su, Wei Wang, Wei-Chen Yang
  • Patent number: 11973260
    Abstract: A light-transmitting antenna includes a substrate, a first and a second conductive pattern. The first and the second conductive pattern is disposed on a first and a second surface of the substrate respectively. The first conductive pattern includes a first feeder unit, a first and a second radiation unit, a first and a second coupling unit and a first parasitic unit. The first feeder unit is connected to the second radiation unit. The first and the second radiation unit are located between the first and the second coupling unit. One side and the other side of the first parasitic unit is connected to the second coupling unit and adjacent to the first coupling unit respectively. The second conductive pattern includes a second feeder unit, a third coupling unit, a second parasitic unit, and a fourth coupling unit.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: April 30, 2024
    Assignee: Industrial Technology Research Institute
    Inventors: Ruo-Lan Chang, Mei-Ju Lee, Cheng-Hua Tsai, Meng-Hsuan Chen, Wei-Chung Chen
  • Publication number: 20240130762
    Abstract: An artificial bone plate unit and an assembleable artificial bone plate are provided. The artificial bone plate unit includes a plate body, multiple connecting pins, connecting holes, drug cavities, and drug-releasing openings. The plate body has two main surfaces and a peripheral surface connected between the two main surfaces. The connecting pins and the connecting holes are formed on the plate body and arranged along the peripheral surface on the plate body. The connecting holes correspond in shape to the connecting pins. The drug cavities are formed in the artificial bone plate unit and are connected to the drug-releasing openings. The artificial bone plate units are connected using the connecting pins and the connecting holes to form the assembleable artificial bone plate. The assembleable artificial bone plate can be bent into the shape of a defect area of the skull, which saves material and time.
    Type: Application
    Filed: October 20, 2022
    Publication date: April 25, 2024
    Inventors: Tung-Kuo TSAI, Keng-Liang OU, Yung-Kang SHEN, Yin-Chung HUANG, Kuo-Sheng HUNG, Yu-Sin OU
  • Publication number: 20240131538
    Abstract: An annular airflow regulating apparatus includes a cup-shaped element and an adjustment element. The cup-shaped element has a bowl and a bottom, integrated to form a first chamber. The bottom has a tapered channel parallel to an axis and penetrating through the bottom. A ring-shaped groove is disposed between the tapered channel and the bottom. The ring-shaped groove has an annular plane perpendicular to the axis. The adjustment element, having a tapered portion and second holes, is movably disposed in the cup-shaped element. The tapered portion protrudes into the tapered channel A tapered annular gap is formed between the tapered portion and the tapered channel. When the adjustment element is moved with respect to the cup-shaped element, a width of the tapered annular gap is varied, and thereupon a flow rate and velocity of the process gas would be varied accordingly.
    Type: Application
    Filed: December 8, 2022
    Publication date: April 25, 2024
    Inventors: CHEN-CHUNG DU, Ming-Jyh Chang, Chang-Yi Chen, Ming-Hau Tsai, Ko-Chieh chao, Yi-Wei Lin
  • Publication number: 20240138272
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first conductive structure over a substrate. A data storage structure overlies the first conductive structure. The data storage structure comprises a first dielectric layer on the first conductive structure and a second dielectric layer on the first dielectric layer. The first dielectric layer comprises a dielectric material and a first dopant having a concentration that changes from a top surface of the first dielectric layer in a direction towards the first conductive structure. A second conductive structure overlies the data storage structure.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Inventors: Fa-Shen Jiang, Cheng-Yuan Tsai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang, Bi-Shen Lee
  • Publication number: 20240134136
    Abstract: An optical transceiver module temperature control device includes a processor, a printed circuit board assembly, an optical transceiver module and a temperature adjustment element. The processor is configured to measure an ambient temperature. The printed circuit board assembly includes a first side and a second side. The first side is opposite to the second side. The optical transceiver module is disposed on the first side of the printed circuit board assembly. The temperature adjustment element is coupled to the processor and disposed on the second side of the printed circuit board assembly. The processor is configured to generate a temperature adjustment signal according to the ambient temperature and an operating temperature range. The temperature adjustment element is configured to perform heat exchange with the printed circuit board assembly according to the temperature adjustment signal to adjust a temperature of the optical transceiver module into the operating temperature range.
    Type: Application
    Filed: October 23, 2023
    Publication date: April 25, 2024
    Applicant: Formerica Optoelectronics, Inc.
    Inventors: Yun-Cheng HUANG, Yi-Nan SHIH, Chih-Chung LIN, Yun-Chin TSAI
  • Patent number: 11961545
    Abstract: Various embodiments of the present disclosure are directed towards a memory device. The memory device has a first transistor having a first source/drain and a second source/drain, where the first source/drain and the second source/drain are disposed in a semiconductor substrate. A dielectric structure is disposed over the semiconductor substrate. A first memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the first memory cell has a first electrode and a second electrode, where the first electrode of the first memory cell is electrically coupled to the first source/drain of the first transistor. A second memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the second memory cell has a first electrode and a second electrode, where the first electrode of the second memory cell is electrically coupled to the second source/drain of the first transistor.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fa-Shen Jiang, Hsia-Wei Chen, Hsun-Chung Kuang, Hai-Dang Trinh, Cheng-Yuan Tsai
  • Publication number: 20240115790
    Abstract: Disclosed is a drainage bottle system comprising: a system housing, a drainage bottle, a drainage tube, a motorless suction device and a liquid detection device, wherein a piezoelectric suction pump of the motorless suction device generates a negative pressure by means of piezoelectric effect to drive the drainage tube to suck and collect a liquid to be detected into the drainage bottle.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 11, 2024
    Applicant: PACIFIC HOSPITAL SUPPLY CO., LTD.
    Inventors: Jung-Yen TSAI, Ming-Chung CHEN, Hsuan-Chiao HO
  • Publication number: 20240120656
    Abstract: A light-transmitting antenna includes a substrate, a first conductive pattern, and a second conductive pattern. The first conductive pattern has a first feeder unit, a first radiation unit, a second radiation unit, and a first connection unit. The first feeder unit and the first connection unit are connected to two sides of the first radiation unit. The first connection unit connects the first radiation unit and the second radiation unit. The second conductive pattern has a second feeder unit, a third radiation unit, a fourth radiation unit, and a second connection unit. The second feeder unit and the second connection unit are connected to two sides of the third radiation unit. The second connection unit connects the third radiation unit and the fourth radiation unit. An orthogonal projection of the second feeder unit on a first surface of the substrate at least partially overlaps the first feeder unit.
    Type: Application
    Filed: December 22, 2022
    Publication date: April 11, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Meng-Hsuan Chen, Cheng-Hua Tsai, Mei-Ju Lee, Ruo-Lan Chang, Wei-Chung Chen
  • Patent number: 11956261
    Abstract: A detection method for a malicious domain name in a domain name system (DNS) and a detection device are provided. The method includes: obtaining network connection data of an electronic device; capturing log data related to at least one domain name from the network connection data; analyzing the log data to generate at least one numerical feature related to the at least one domain name; inputting the at least one numerical feature into a multi-type prediction model, which includes a first data model and a second data model; and predicting whether a malicious domain name related to a malware or a phishing website exists in the at least one domain name by the multi-type prediction model according to the at least one numerical feature.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: April 9, 2024
    Assignee: Acer Cyber Security Incorporated
    Inventors: Chiung-Ying Huang, Yi-Chung Tseng, Ming-Kung Sun, Tung-Lin Tsai
  • Patent number: 11947886
    Abstract: A development system and a method of an offline software-in-the-loop simulation are disclosed. A common firmware architecture generates a chip control program. The common firmware architecture has an application layer and a hardware abstraction layer. The application layer has a configuration header file and a product program. A processing program required by a peripheral module is added to the hardware abstraction layer during compiling. The chip control program is provided to a controller chip or a circuit simulation software to be executed to control the product-related circuit through controlling the peripheral module.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: April 2, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yu-Jen Lin, Chang-Chung Lin, Chia-Wei Chu, Terng-Wei Tsai, Feng-Hsuan Tung
  • Publication number: 20240104021
    Abstract: Embodiments are for processor cross-core cache line contention management. A computer-implemented method includes sending a cross-invalidate command to one or more caches based on receiving a cache state change request for a cache line in a symmetric multiprocessing system and determining a retry delay based on receiving a cross-invalidate reject response from at least one of the one or more caches. The computer-implemented method also includes waiting until a retry delay period associated with the retry delay has elapsed to resend the cross-invalidate command to the one or more caches and granting the cache state change request for the cache line based on receiving a cross-invalidate accept response from the one or more caches.
    Type: Application
    Filed: September 23, 2022
    Publication date: March 28, 2024
    Inventors: Michael Joseph Cadigan, JR., Gregory William Alexander, Deanna Postles Dunn Berger, Timothy Bronson, Chung-Lung K. Shum, Aaron Tsai
  • Publication number: 20240105664
    Abstract: A package structure includes a first RDL, an adhesive layer and a first electronic component. Upper bumps and conductive pads are provided on a first upper surface and a first lower surface of the first RDL, respectively. The adhesive layer is located on the first upper surface of the first RDL and surrounds the upper bumps. The first electronic component is mounted on the adhesive layer and includes conductors which are visible from an active surface of the first electronic component and joined to the upper bumps, the active surface of the first electronic component faces toward the first upper surface of the first RDL. Two adhesive surfaces of the adhesive layer are adhered to the first upper surface of the first RDL and the active surface of the first electronic component, respectively.
    Type: Application
    Filed: August 16, 2023
    Publication date: March 28, 2024
    Inventors: Yu-Chung Huang, Hsin-Yen Tsai, Fa-Chung Chen, Cheng-Fan Lin, Chen-Yu Wang
  • Publication number: 20240105879
    Abstract: A light-emitting diode and a manufacturing method thereof are provided. The manufacturing method includes following steps. First, an LED wafer is provided. The LED wafer includes a substrate and a light-emitting semiconductor stacking structure positioned on the surface of the substrate. The light-emitting semiconductor stacking structure includes a first type semiconductor layer, an active layer, and a second type semiconductor layer from a side of the substrate. Second, dicing lanes are defined on the upper surface of the LED wafer. Third, dicing is performed along the dicing lanes of the substrate using a laser. The laser is focused on the lower surface of the substrate to form a surface hole and focused inside the substrate to form an internal hole. The diameter of the surface hole is greater than the diameter of the internal hole. Fourth, the LED wafer is separated into LED chips along the dicing lanes.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 28, 2024
    Applicant: Quanzhou sanan semiconductor technology Co., Ltd.
    Inventors: TSUNG-MING LIN, CHUNG-YING CHANG, YI-JUI HUANG, YU-TSAI TENG
  • Patent number: 11939212
    Abstract: A MEMS device is provided. The MEMS device includes a substrate having at least one contact, a first dielectric layer disposed on the substrate, at least one metal layer disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer and the metal layer and having a recess structure, and a structure layer disposed on the second dielectric layer and having an opening. The opening is disposed on and corresponds to the recess structure, and the cross-sectional area at the bottom of the opening is smaller than the cross-sectional area at the top of the recess structure. The MEMS device also includes a sealing layer, and at least a portion of the sealing layer is disposed in the opening and the recess structure. The second dielectric layer, the structure layer, and the sealing layer define a chamber.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: March 26, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Heng-Chung Chang, Jhih-Jie Huang, Chih-Ya Tsai, Jing-Yuan Lin
  • Patent number: 11942373
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin, a second fin and a third fin therebetween. A first insulating structure includes a first insulating layer formed between the first and third fins, a capping structure covering the first insulating layer, a first insulating liner covering sidewall surfaces of the first insulating layer and the capping structure and a bottom surface of the first insulating layer, and a second insulating liner formed between the first insulating liner and the first fin and between the first insulating liner and the third fin. The second insulating structure includes a second insulating layer formed between the second fin and the third fin and a third insulating liner formed between the second insulating layer and the second fin and between the second insulating layer and the third fin.
    Type: Grant
    Filed: May 10, 2023
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chu-An Lee, Chen-Hao Wu, Peng-Chung Jangjian, Chun-Wen Hsiao, Teng-Chun Tsai, Huang-Lin Chao
  • Patent number: RE49901
    Abstract: An electrical connector includes an insulative housing defining a front cavity for receiving and a rear cavity, a terminal assembly assembled in the rear cavity, and a ground member. The terminal assembly includes an upper terminal module, a lower terminal module sandwiching a shielding module therebetween. Said The upper terminal module includes a pair of upper ground terminals. Said The lower terminal module includes a plurality of lower ground terminals. Said The shielding module includes a metallic shielding plate. The ground member is associated with the shielding module to mechanically and electrically connect at least one of the upper ground terminals and the lower ground terminals with the shielding plate.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: April 2, 2024
    Assignee: FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: Terrance F. Little, Chih-Hsien Chou, Chun-Hsiung Hsu, Kuei-Chung Tsai