Abstract: A base structure in an electroplating system is provided. The base structure includes: includes: an annular member; a contact ring attached to an inner surface of the annular member and configured to be electrically connected to a wafer in an electroplating process; and a pair of shield structures attached to an upper surface of the annular member and extending in an vertical direction. Each of the pair of shield structures includes: a curved plate comprising a plurality of discharging openings, wherein plating solution residual is discharged through the plurality of discharging openings in a cleaning procedure; and a plurality of bevels, each of the plurality of bevels corresponding to each of the plurality of discharging openings and configured to guide the plating solution residual toward the corresponding discharging opening in the cleaning procedure.

Abstract: A public-key scheme of Homomorphic Encryption (HE) in the framework Quotient Algebra Partition (QAP) comprises: encryption, computation and decryption. With the data receiver choosing a partition or a QAP, [n, k, C], a public key Keypub=(VQen, ) and a private key Keypriv=†P\ are produced, where VQen is the product of an n-qubit permutation V and an n-qubit encoding operator Qen, an error generator randomly provides a dressed operator ?=V†EV of spinor error E of [n, k, C]. Then, by Keypub, the sender can encode his k-qubit plaintext |x into an n-qubit ciphertext |?en, which is transmitted to the cloud. The receiver prepares the instruction of encoded computation Uen=PV†Qen† for a given k-qubit action M and sends to cloud, where is the error-correction operator of [n, k, C], =I2n?k?M the tensor product of the (n?k)-qubit identity I2n?k and M, and V†Qen† and P the complex-transposes of VQen and †P† respectively.

Abstract: The method of constructing QAP-based Homomorphic Encryption (HE) in the semi-public setting is introduced, which comprises: encryption, computation, and decryption. The data receiver produces a semi-public key Keys-pub.The data provider can encode his k-qubit plaintext |x to a k-qubit ciphertext |?en=QP|x via a k-qubit invertible operator QP randomly generated by Keys-pub. From the provider, the message En(?p) of QP encoded by a cryptosystem Gcrypt in Keys-pub is transmitted to the receiver through a small-resource communication channel and the ciphertext |?en is conveyed to the cloud. The receiver creates the instruction of encoded computation Uen=PMQP and transports to the cloud, where M is the required k-qubit arithmetic operation, P a k-qubit permutation, and a k-qubit operator to mingle with M. According the instruction, the cloud performs the encrypted evaluation Uen|?en and transfer to the receiver.

Abstract: The present disclosure provides an image processing circuit including a neural network processor, a background processing circuit and a blending circuit. The neural network processor is configured to process input image data to determine whether the input image data has a predetermined object so as to generate to heat map. The background processing circuit blurs the input image data to generate blurred image data. The blending circuit blends the input image data and the blurred image data according to the heat map to generate output image data.

Abstract: A three-dimensional device structure includes a die including a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, a through silicon via (TSV) structure that extends through the semiconductor substrate and electrically contacts a metal feature of the interconnect structure, and an integrated passive device (IPD) embedded in the semiconductor substrate and electrically connected to the TSV structure.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a substrate. A resistor overlies the substrate. The resistor comprises a first metal nitride structure, a second metal nitride structure spaced from the first metal nitride structure, and a metal structure disposed between the first metal nitride structure and the second metal nitride structure. A first dielectric structure is disposed over the substrate and the resistor.

Abstract: A semiconductor device includes a first semiconductor die mounted on a substrate, a second semiconductor die mounted on the substrate and separated from the first semiconductor die, a first dielectric material between the first semiconductor die and the second semiconductor die and having a first density, and a column of second dielectric material in the first dielectric material, the second dielectric material having a second density different than the first density, and the second dielectric material including a void region.

Abstract: A three-dimensional device structure includes a first die including a first semiconductor substrate, a second die disposed on the first die and including a second semiconductor substrate, a dielectric encapsulation (DE) layer disposed on the first die and surrounding the second die, a redistribution layer structure disposed on the second die and the DE layer, and an integrated passive device (IPD) embedded in the DE layer and electrically connected to the first die and the redistribution layer structure.

Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a bottom electrode disposed over a lower interconnect within a lower inter-level dielectric (ILD) layer over a substrate. A data storage structure is over the bottom electrode. A first top electrode layer is disposed over the data storage structure, and a second top electrode layer is on the first top electrode layer. The second top electrode layer is less susceptible to oxidation than the first top electrode layer. A top electrode via is over and electrically coupled to the second top electrode layer.

Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a co-doped data storage structure. A bottom electrode overlies a substrate and a top electrode overlies the bottom electrode. The data storage structure is disposed between the top and bottom electrodes. The data storage structure comprises a dielectric material doped with a first dopant and a second dopant.

Abstract: An electrical connector includes an insulating body, a first terminal group having a signal terminal pair and a ground terminal arranged on one side of the signal terminal pair, each signal terminal having a tail portion, a contact portion, and a body portion, the body portion having a covering portion and a free portion exposed to air, wherein there is a first center distance between the contact portions of the signal terminal pair, there is a second center distance between the free portions, and there is a third center distance between the covering parts, and a second terminal group forming a first mating port with the first terminal group, wherein the second center distance is smaller than the first center distance, and the third center distance is greater than the second center distance.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a memory device. The method includes forming a bottom electrode over a substrate. A data storage structure is formed on the bottom electrode. The data storage structure comprises a first atomic percentage of a first dopant and a second atomic percentage of a second dopant. The first atomic percentage is different from the second atomic percentage. A top electrode is formed on the data storage structure.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a memory device. The method includes forming a data storage layer on a bottom electrode layer over a substrate, forming a first top electrode layer over the data storage layer, and forming a second top electrode layer over the first top electrode layer. The first top electrode layer has a smaller corrosion potential than the second top electrode layer. A first patterning process is performed on the first top electrode layer and the second top electrode layer to define a multi-layer top electrode. A second patterning process is performed on the data storage layer and the bottom electrode layer to define a data storage structure and a bottom electrode.

Abstract: A method of fabricating a photonic device includes: forming a photonic device structure that includes a SOI substrate, which includes a bulk substrate layer, a buried oxide layer on the bulk substrate layer and an active semiconductor layer on the buried oxide layer; forming an electrically conducting layer in electrical contact of the buried oxide layer, and forming a BEOL structure on a surface of the active silicon layer.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

Abstract: A die includes: a semiconductor substrate having a front side and an opposing backside; a dielectric structure including a substrate oxide layer disposed on the front side of the semiconductor substrate and interlayer dielectric (ILD) layers disposed on the substrate oxide layer; an interconnect structure disposed in the dielectric structure; a through-silicon via (TSV) structure extending in a vertical direction from the backside of the semiconductor substrate through the front side of the semiconductor substrate, such that a first end of the TSV structure is disposed in the interconnect structure; and a TSV barrier structure including a barrier line that contacts the first end of the TSV structure, and a first seal ring disposed in the substrate oxide layer and that that surrounds the TSV structure in a lateral direction perpendicular to the vertical direction.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an interconnect structure disposed over a substrate. The interconnect structure includes a plurality of interconnect layers disposed within a dielectric structure. A bond pad structure is disposed over the interconnect structure. The bond pad structure includes a contact layer. A first masking layer including a metal-oxide is disposed over the bond pad structure. The first masking layer has interior sidewalls arranged directly over the bond pad structure to define an opening. A conductive bump is arranged within the opening and on the contact layer.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a lower conductive structure over a substrate. A data storage structure is formed on the lower conductive structure. A bandgap of the data storage structure discretely increases or decreases at least two times from a top surface of the data storage structure in a direction towards the substrate. An upper conductive structure is formed on the data storage structure.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.