Abstract: A three-dimensional device structure includes a first die including a first semiconductor substrate, a second die disposed on the first die and including a second semiconductor substrate, a dielectric encapsulation (DE) layer disposed on the first die and surrounding the second die, a redistribution layer structure disposed on the second die and the DE layer, and an integrated passive device (IPD) embedded in the DE layer and electrically connected to the first die and the redistribution layer structure.

Abstract: An energy storage apparatus includes a energy storage for storing water and compressed gas; a concrete layer surrounded the energy storage; an inner protection layer arranged on an inner surface of the energy storage.

Abstract: An apparatus having a first portion including a first front wall, a first rear wall, and a bottom wall integrally coupled to the first front wall and the first rear wall, and pivotal pin structures integrally coupled to and extending from the first rear wall. The apparatus includes a second portion having a second front wall, a second rear wall, and a top wall integrally coupled to the second front wall and the second rear wall, and pin holders integrally coupled to and extending from the second rear wall and at an offset angle with reference to the top wall. The pivotal pin structure includes a base support connected to the first rear wall and a shaft connected to the base support, and the pin holder defines an opening sized and shaped to accept the shaft. The first and second portions are sized and shaped to be pivotally movable between open and closed configurations.

Abstract: A three-dimensional device structure includes a die including a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, a through silicon via (TSV) structure that extends through the semiconductor substrate and electrically contacts a metal feature of the interconnect structure, and an integrated passive device (IPD) embedded in the semiconductor substrate and electrically connected to the TSV structure.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a substrate. A resistor overlies the substrate. The resistor comprises a first metal nitride structure, a second metal nitride structure spaced from the first metal nitride structure, and a metal structure disposed between the first metal nitride structure and the second metal nitride structure. A first dielectric structure is disposed over the substrate and the resistor.

Abstract: The invention provides a semiconductor manufacturing method, which comprises providing a substrate with a photoresist layer, forming a hydrophilic film on a surface of the photoresist layer by a spin coating process, and forming a top anti-reflective coating (TARC) on the surface of the hydrophilic film.

Abstract: A die includes: a semiconductor substrate having a front side and an opposing back side; a dielectric structure including a substrate oxide layer disposed on the front side of the semiconductor substrate and interlayer dielectric (ILD) layers disposed on the substrate oxide layer; an interconnect structure disposed in the dielectric structure; a through-silicon via (TSV) structure extending in a vertical direction from the back side of the semiconductor substrate through the front side of the semiconductor substrate, such that a first end of the TSV structure is disposed in the interconnect structure; and a TSV barrier structure including a barrier line that contacts the first end of the TSV structure, and a first seal ring disposed in the substrate oxide layer and that surrounds the TSV structure in a lateral direction perpendicular to the vertical direction.

Abstract: A three-dimensional device structure includes a die including a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, a through silicon via (TSV) structure that extends through the semiconductor substrate and electrically contacts a metal feature of the interconnect structure, and an integrated passive device (IPD) embedded in the semiconductor substrate and electrically connected to the TSV structure.

Abstract: A semiconductor device includes a first semiconductor die mounted on a substrate, a second semiconductor die mounted on the substrate and separated from the first semiconductor die, a first dielectric material between the first semiconductor die and the second semiconductor die and having a first density, and a column of second dielectric material in the first dielectric material, the second dielectric material having a second density different than the first density, and the second dielectric material including a void region.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. A first conductive structure overlies a substrate. A second conductive structure overlies the first conductive structure. A data storage structure is disposed between the first and second conductive structures. The data storage structure includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. Respective bandgaps of the first, second, and third dielectric layers are different from one another.

Abstract: A method of evaluating core muscles by bioimpedance technology, includes the steps of: (a) measuring the resistance and reactance of a subject by a bioimpedance measuring instrument, and obtaining the subject's age, gender, and impedance factor (h2/Z), and (b) calculating the subject's core muscles by the following formula: BIA=a?b×age+c×h2/Z+d×Sex. Thereby, the present invention measures the cross-sectional area of the core muscles by means of bioimpedance analysis. The core muscles can be evaluated by the cross-sectional area of the core muscles, which can effectively reduce the measurement cost, reduce the measurement time and improve the convenience of measurement.

Abstract: A semiconductor device includes a first semiconductor die mounted on a substrate, a second semiconductor die mounted on the substrate and separated from the first semiconductor die, a first dielectric material between the first semiconductor die and the second semiconductor die and having a first density, and a column of second dielectric material in the first dielectric material, the second dielectric material having a second density different than the first density, and the second dielectric material including a void region.

Abstract: The method of constructing QAP-based Homomorphic Encryption (HE) in the semi-public setting is introduced, which comprises: encryption, computation, and decryption. The data receiver produces a semi-public key Keys-pub. The data provider can encode his k-qubit plaintext |x to a k-qubit ciphertext |?en=QP|x via a k-qubit invertible operator QP randomly generated by Keys-pub. From the provider, the message En(?p) of QP encoded by a cryptosystem Gcrypt in Keys-pub is transmitted to the receiver through a small-resource communication channel and the ciphertext |?en is conveyed to the cloud. The receiver creates the instruction of encoded computation Uen=PMQP and transports to the cloud, where M is the required k-qubit arithmetic operation, P a k-qubit permutation, and a k-qubit operator to mingle with M. According the instruction, the cloud performs the encrypted evaluation Uen|?en and transfer to the receiver.

Abstract: A method for manufacturing reflective structure is provided. The method includes the operations as follows. A metallization structure is received. A plurality of conductive pads are formed over the metallization structure. A plurality of dielectric stacks are formed over the conductive pads, respectively, wherein the thicknesses of the dielectric stacks are different. The dielectric stacks are isolated by forming a plurality of trenches over a plurality of intervals between each two adjacent dielectric stacks.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a lower conductive structure over a substrate. A data storage structure is formed on the lower conductive structure. A bandgap of the data storage structure discretely increases or decreases at least two times from a top surface of the data storage structure in a direction towards the substrate. An upper conductive structure is formed on the data storage structure.

Abstract: A public-key scheme of Homomorphic Encryption (HE) in the framework Quotient Algebra Partition (QAP) comprises: encryption, computation and decryption. With the data receiver choosing a partition or a QAP, [n, k, C], a public key Keypub=(VQen, Gen?) and a private key Keypriv=†P† are produced, where VQen is the product of an n-qubit permutation V and an n-qubit encoding operator Qen, Gen? an error generator randomly provides a dressed operator ?=V†EV spinor error E of [n, k, C]. Then, by Keypub, the sender can encode his k-qubit plaintext Ix) into an n-qubit ciphertext |?en, which is transmitted to the cloud. The receiver prepares the instruction of encoded computation Uen=PV†Qen† for a given k-qubit action M and sends to cloud, where is the error-correction operator of [n, k, C], =I2n?k?M the tensor product of the (n?k)-qubit identity I2n?k and M , and V†Q†en and P the complex-transposes of VQen and †P† respectively.

Abstract: A method of constructing a procedural threshold in quotient algebra partition-based fault tolerance quantum computation, which is based on the framework of quotient algebra partition (QAP) applied in the fault tolerance quantum computation (FTQC), wherein an n-qubit fault tolerant encode of a k-qubit quantum gate M, is feasible to a threshold, wherein the method comprises: preparing a quantum code, with a stabilizer; creating an n-qubit encoding, in the quantum code, and obtaining an n-qubit fault tolerant encode of M; factorizing each encoded component, of this n-qubit fault tolerant encode; and producing a detection-correction operator by placing n-k ancilla qubits with the original system of n qubits, wherein the detection-correction operator comprises a conditional detection operator and a conditional correction operator to remove r-qubit spinor error.

Abstract: A method of designing a multi-party system in quotient algebra partition-based homomorphic encryption (QAPHE), which is based on the framework of quotient algebra partition (QAP) and the computation of homomorphic encryption (HE), wherein the method comprises: increasing single model provider A to multiple ones, wherein the number of the multiple model providers is L and let A1?i?L and L?2; increasing single data provider B to multiple ones, wherein the number of the multiple data providers is R and let B1?j?R and R?2; and encoding plaintexts, each of which is of kj qubits, from all data providers into ciphertexts respectively; aggregating the ciphertexts by a form of tensor product and generating an encoded state for computation; and preparing a model operation to conduct the encrypted computation via an encoded operator and the encoded state in a cloud. The method can improve the security of public-key/semi-public-key system and be applied to a threshold HE or a multi-key HE to solve actual problems.

Abstract: The present inventive concept discloses a method of designing a one-way computational system in QAP-based homomorphic encryption applied to the n-qubit encode operations of a k-qubit action M for public-key and semi-public-key schemes respectively, n?k, wherein the method comprises: preparing a tensor-product operator =I2n-k?M=12 and decomposing it into two parts, wherein is composed of elementary gates, and let =1† and 2=; providing a correction operator, =12 for public-key and =I2k for semi-public-key, and an encoding operator, Qen†V†=W1W2 for public-key and Qp†=W1W2 for semi-public-key, both composed of elementary gates; providing appropriate permutations P, P0 and P1, while P0=P1 for semi-public-key, to obey the nilpotent condition PW1P0=I for the identity operator; through process of merging operators according to sets of identities of gates, including Id-GateELIM, Id-GateEx and Id-GateREP, there obtain the mixed encode for public-key scheme, Uen=PQen†V†=(P1†W1†21W1P1)(P1†P0)(P0†2W1P0) (P0†W2), and that