Abstract: An image processing method and an image processing apparatus are provided. After receiving an image signal, the image and apparatus according to the invention first judge whether a target block in the image signal includes a non-chroma line. If the judging result is YES, a first edge detection procedure will be performed on the non-chroma line. If the judging result is NO, a second edge detection procedure will be performed on the target block.

Abstract: A hand-held wireless device with the PCI Express interface has a body, a PCI Express connector formed on end of the body, a control module mounted in the body and connected to the PCI Express connector, and multiple operating buttons mounted on the body. The control module has a wireless communication unit and a digital signal processor for wirelessly receiving and transmitting signals and processing data. The hand-held wireless device can be inserted to a PCI Express port of an electronic apparatus. When in use, the hand-held wireless device is detached from the electronic apparatus and communicates with the electronic apparatus through the wireless communication unit. The hand-held wireless device can be used as a wireless telephone, a game pad or an input device.

Abstract: A multimode-compressive overdrive circuit includes a plurality of calculation units, a determination unit and a multimode encoding unit. The calculation units receive display data, and generate a plurality of image error values according to a plurality of compression modes. The determination unit, coupled to the calculation units, generates a best-compression mode signal according to the image error values. The multimode encoding unit, coupled to the determination unit, multimode-compresses the display data in response to the best-compression mode signal.

Abstract: One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM capacitor embedded isolation structure.

Abstract: A video processing system is presented that interleaves video data. In accordance with some embodiments of the present invention, data from a first field is placed in a frame and is augmented with pixel values in adjacent alternate rows of the frame with pixel values determined from the pixel values in the first field data and pixel values from the second field data.

Abstract: One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM capacitor embedded isolation structure.

Abstract: A method for producing a memory with high coupling ratio is provided. First, a shallow trench isolation is formed on a substrate to define an active area. Second, a spacer is formed at the sidewall of the shallow trench isolation. Third, the shallow trench isolation is etched such that the top of the spacer is higher than the surface of the shallow trench isolation. Fourth, a tunnel oxide is formed on the active area. Finally, a floating gate is formed on the tunnel oxide.

Abstract: A memory structure comprising a plurality of memory cells is described. Each memory cell comprises a substrate, a shallow trench isolation, a spacer, a tunnel oxide, and a floating gate. The shallow trench isolation in the substrate is used to define an active area. The spacer is at the sidewall of the shallow trench isolation and is higher than the shallow trench isolation. The tunnel oxide is on the active area. The floating gate is on the tunnel oxide.

Abstract: One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM capacitor embedded isolation structure.

Abstract: A new method and structure is provided for the creation of a 1T-RAM cell. Shallow Trench Isolation (STI) regions are provided over a substrate. A 3D capacitor area is defined over the substrate, a patterned layer of polysilicon or HSG polysilicon is created aligned with the 3D capacitor area, providing the bottom plate of a 3D capacitor. Gate oxide is grown to form a dielectric for CMOS gate electrodes and the 3D capacitor dielectric. A patterned layer of polysilicon is created, defining gate electrodes and 3D capacitor upper plates.

Abstract: A wafer has a substrate defined with a first region and a second region. An ONO layer, a first silicon layer, and a silicon nitride layer are formed on the substrate in sequence. Then the ONO layer, the first silicon layer, and the silicon nitride layer disposed on the second region are removed. At least one gate oxide layer is formed on the second region and a second silicon layer is deposited on the wafer. After that, a photo-etching process is performed to remove the second silicon layer and the silicon nitride layer on the first region. At least a third silicon layer is formed on the wafer. Photo-etching processes and a plurality of ion implantation processes are then performed to form a gate, a drain, and a source of each MOS transistor on the substrate.

Abstract: A wafer has a substrate defined with a first region and a second region. An ONO layer, a first silicon layer, and a silicon nitride layer are formed on the substrate in sequence. Then the ONO layer, the first silicon layer, and the silicon nitride layer disposed on the second region are removed. At least one gate oxide layer is formed on the second region and a second silicon layer is deposited on the wafer. After that, a photo-etching process is performed to remove the second silicon layer and the silicon nitride layer on the first region. At least a third silicon layer is formed on the wafer. Photo-etching processes and a plurality of ion implantation processes are then performed to form a gate, a drain, and a source of each MOS transistor on the substrate.

Abstract: A new method and structure is provided for the creation of a 1T-RAM cell. Masking layers for Shallow Trench Isolation (STI) regions are provided over a layer of pad oxide over a substrate, the STI trenches are etched in the substrate, filled with field isolation oxide which is planarized. A 3D capacitor area is defined over the substrate, a layer of polysilicon or HSG polysilicon is deposited over exposed surfaces of the defined 3D capacitor and over the STI etch mask. A protective layer of photoresist or BARC is deposited over the layer of polysilicon or HSG polysilicon aligned with the 3D capacitor area. The exposited layer of polysilicon or HSG polysilicon is removed, creating the bottom plate of a capacitor. The STI mask is removed, including the layer of pad oxide, exposing the substrate. SAC oxide is grown over the exposed substrate, n/p well impurity implants are performed into the substrate.

Abstract: The gate for at least one transistor is formed on the surface of the semiconductor substrate and the gate is utilized as a mask to form a lightly doped drain of the transistor. A low thermal budget deposition process is performed to form a silicon nitride layer on the surface or the semiconductor substrate. An ion implantation process is performed to implant fluorine atoms into the silicon nitride layer. After that, an etching process is performed to form a spacer in the periphery of the gate. Finally, a source/drain of the transistor is formed. The implanted fluorine atoms bond with the hydrogen atoms and keep them from becoming interface trapped charges. This increases the threshold voltage stability of the transistor.

Abstract: The gate for at least one transistor is formed on the surface of the semiconductor substrate and the gate is utilized as a mask to form a lightly doped drain of the transistor. A low thermal budget deposition process is performed to form a silicon nitride layer on the surface or the semiconductor substrate. An ion implantation process is performed to implant fluorine atoms into the silicon nitride layer. After that, an etching process is performed to form a spacer in the periphery of the gate. Finally, a source/drain of the transistor is formed. The implanted fluorine atoms bond with the hydrogen atoms and keep them from becoming interface trapped charges. This increases the threshold voltage stability of the transistor.

Abstract: A method of manufacturing a MOS transistor. A substrate having a gate oxide layer, a gate electrode and spacers attached to the sidewalls of the gate electrode is provided. A source/drain (S/D) implantation is conducted to form a source/drain region in the substrate on each side of the gate electrode. A self-aligned silicide (Salicide) process is carried out to form a self-aligned silicide layer over the exposed gate electrode and source/drain region. A silicon nitride layer serving as an etching stop is formed over the substrate. A fluoride blanket implantation of the silicon nitride etching stop layer is carried out using an implantation dosage of about 5×1013 ˜5×1014 cm−2 and at an implantation energy level between 2 KeV˜5 KeV. The fluorides implanted into the silicon nitride layer capture hydrogen within the silicon nitride layer, thereby reducing free hydrogen concentration and increasing threshold voltage stability of the MOS transistor.

Abstract: A method of manufacturing a MOS transistor. A substrate having a gate oxide layer, a gate electrode and spacers attached to the sidewalls of the gate electrode is provided. A source/drain (S/D) implantation is conducted to form a source/drain region in the substrate on each side of the gate electrode. A self-aligned silicide (Salicide) process is carried out to form a self-aligned silicide layer over the exposed gate electrode and source/drain region. A silicon nitride layer serving as an etching stop is formed over the substrate. A fluoride blanket implantation of the silicon nitride etching stop layer is carried out using an implantation dosage of about 5×1013˜5×1014 cm2 and at an implantation energy level between 2 KeV˜5 KeV. The fluorides implanted into the silicon nitride layer capture hydrogen within the silicon nitride layer, thereby reducing free hydrogen concentration and increasing threshold voltage stability of the MOS transistor.

Abstract: A method of manufacturing a MOS transistor. A substrate having a gate oxide layer, a gate electrode and spacers attached to the sidewalls of the gate electrode is provided. A source/drain (S/D) implantation is conducted to form a source/drain region in the substrate on each side of the gate electrode. A self-aligned silicide (Salicide) process is carried out to form a self-aligned silicide layer over the exposed gate electrode and source/drain region. A silicon nitride layer serving as an etching stop is formed over the substrate. A fluoride blanket implantation of the silicon nitride etching stop layer is carried out using an implantation dosage of about 5×1013˜5×1014 cm−2 and at an implantation energy level between 2 KeV˜5 KeV. The fluorides implanted into the silicon nitride layer capture hydrogen within the silicon nitride layer, thereby reducing free hydrogen concentration and increasing threshold voltage stability of the MOS transistor.

Abstract: This invention relates to a method of forming a word line, more particularly, to the method of forming a word line in an embedded dynamic random access memory (eDRAM). The present invention uses a sandwich structure in silicon (Si)/tungsten silicon (WSi)/buffer layer to be the structure of the word line in the embedded dynamic random access memory to keep the enough thickness of the nitride layer, which is on the gate, and to proceed the self-aligned contact process in the embedded dynamic random access memory region in the following process to increase the efficiency of the process. The gate, which is formed by using the present invention method and is proceed the metal salicide process in the logic region that is in the embedded dynamic random access memory, will keep the low resistance of the word line and will increase the efficiency of the embedded dynamic random access memory.

Abstract: A Reflecting panel structure of reflective liquid crystal display, in which the photoresistor layer laid on the substrate board is formed with multiple rough etched bottom faces and multiple protuberances. The protuberances protrude beyond the multiple etched bottom faces. The metal film disposed over the photoresistor layer is formed with multiple scattering bottom faces on the etched bottom faces thereof. The scattering bottom faces being composed of multiple irregular scattering protrusions for reflecting light beam in different directions.