Abstract: An image processing method is used for determining a motion vector of a covered/uncovered area within an interpolated picture when picture interpolation is performed. The interpolated picture includes a plurality of blocks, and the image processing method includes: generating a first motion vector and a second motion vector of a block within the interpolated picture; determining which one of the covered and uncovered areas the block is located in, and calculating a reference vector according to the first and second motion vectors; and determining a motion vector of the block according to the reference vector, wherein the reference vector is obtained from vector calculation of the first and second motion vectors using the principle of similar triangles.

Abstract: An image processing method for determining a motion vector of an interpolated block in a covered/uncovered area of an interpolated picture. The method comprises determining image difference values of successive blocks according to original motion vectors of the successive blocks; determining first and second motion vectors for the successive blocks according to the image difference values, wherein the first and the second motion vector of one of the successive blocks are the original motion vectors of two blocks located in both side of a block having a maximum image difference value; determining a starting point of the interpolated block according to the first and the second motion vectors of the successive blocks; and selecting one of the first and the second motion vectors of the interpolated block as the motion vector of the interpolated block according to the starting point and a starting point in a previous interpolated picture.

Abstract: An image processing method includes: detecting a motion vector of a source image block within a first video image to determine a flag value of the source image block, wherein the flag is used for indicating whether image content of the source image block correspondingly includes sight variations; and determining a target motion vector used for an interpolated image block according to the flag value.

Abstract: A method and an associated apparatus for determining a motion vector are disclosed. The method includes performing block matching for a first block where an interpolated block is located according to the first frame and the second frame to generate a first candidate motion vector of the interpolated block, performing block matching for a second block where the interpolated block is located according to the first frame and the second frame to generate a second candidate motion vector of the interpolated block, and determining a target motion vector of the interpolated block according to either of the first motion vector and the second candidate motion vector.

Abstract: An image processing circuit includes a compression circuit, a plurality of first line buffers, a decompression circuit, and a motion estimation/compensation circuit. The compression circuit receives source image data and compresses the received source image data to generate a compressed image data. The first line buffers, coupled to the compression circuit, sequentially receive the compressed image data and buffer the compressed image data. The decompression circuit, coupled to the first line buffers, decompresses the compressed image data to generate a decompressed image data. The motion estimation/compression circuit, coupled to the decompression circuit, performs motion estimation/compensation according to the decompressed image data.

Abstract: The invention provides a video processing method, which includes: performing motion estimation upon the target image block and a plurality of reference image blocks to calculate a plurality of block matching differences; determining a minimum block matching difference from the plurality of the block matching differences; comparing the minimum block matching difference with at least one of the reference block matching differences to obtain at least a comparison result; and according to the at least a comparison result, selectively determining a target motion vector of the target image block referred to a motion vector of at least a neighboring image block of the target image block or a motion vector corresponding to the minimum block matching difference.

Abstract: An image processing circuit generating a frame according to a plurality of fields including at least first, second and third fields, comprises a memory unit and a de-interlacing unit. The memory unit stores the first and second fields. The de-interlacing unit receives the third field, and reads the first and second fields from the memory to generate a de-interlaced frame accordingly.

Abstract: An image processing method of generating a target image block of a position to be currently interpolated in an interpolated frame between two frames includes: performing a motion estimation for generating a motion vector by referring to a plurality of image blocks of the two frames and generating a first image block according to the motion vector; generating a second image block according to two image blocks which are respectively in the two frames and both correspond to the position to be currently interpolated; and generating the target image block according to the first image block and the second image block.

Abstract: An image processing method includes generating a block matching result by performing a block matching operation according to a plurality of image blocks in the horizontal direction without referring to an image block in the vertical or other directions and performing an image processing operation according to the block matching result of the block matching operation.

Abstract: A memory structure comprising a plurality of memory cells is described. Each memory cell comprises a substrate, a shallow trench isolation, a spacer, a tunnel oxide, and a floating gate. The shallow trench isolation in the substrate is used to define an active area. The spacer is at the sidewall of the shallow trench isolation and is higher than the shallow trench isolation. The tunnel oxide is on the active area. The floating gate is on the tunnel oxide.

Abstract: An image processing method and an image processing apparatus are provided. After receiving an image signal, the image and apparatus according to the invention first judge whether a target block in the image signal includes a non-chroma line. If the judging result is YES, a first edge detection procedure will be performed on the non-chroma line. If the judging result is NO, a second edge detection procedure will be performed on the target block.

Abstract: A multimode-compressive overdrive circuit includes a plurality of calculation units, a determination unit and a multimode encoding unit. The calculation units receive display data, and generate a plurality of image error values according to a plurality of compression modes. The determination unit, coupled to the calculation units, generates a best-compression mode signal according to the image error values. The multimode encoding unit, coupled to the determination unit, multimode-compresses the display data in response to the best-compression mode signal.

Abstract: A hand-held wireless device with the PCI Express interface has a body, a PCI Express connector formed on end of the body, a control module mounted in the body and connected to the PCI Express connector, and multiple operating buttons mounted on the body. The control module has a wireless communication unit and a digital signal processor for wirelessly receiving and transmitting signals and processing data. The hand-held wireless device can be inserted to a PCI Express port of an electronic apparatus. When in use, the hand-held wireless device is detached from the electronic apparatus and communicates with the electronic apparatus through the wireless communication unit. The hand-held wireless device can be used as a wireless telephone, a game pad or an input device.

Abstract: One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM capacitor embedded isolation structure.

Abstract: A video processing system is presented that interleaves video data. In accordance with some embodiments of the present invention, data from a first field is placed in a frame and is augmented with pixel values in adjacent alternate rows of the frame with pixel values determined from the pixel values in the first field data and pixel values from the second field data.

Abstract: One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM capacitor embedded isolation structure.

Abstract: A method for producing a memory with high coupling ratio is provided. First, a shallow trench isolation is formed on a substrate to define an active area. Second, a spacer is formed at the sidewall of the shallow trench isolation. Third, the shallow trench isolation is etched such that the top of the spacer is higher than the surface of the shallow trench isolation. Fourth, a tunnel oxide is formed on the active area. Finally, a floating gate is formed on the tunnel oxide.

Abstract: A memory structure comprising a plurality of memory cells is described. Each memory cell comprises a substrate, a shallow trench isolation, a spacer, a tunnel oxide, and a floating gate. The shallow trench isolation in the substrate is used to define an active area. The spacer is at the sidewall of the shallow trench isolation and is higher than the shallow trench isolation. The tunnel oxide is on the active area. The floating gate is on the tunnel oxide.

Abstract: One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM capacitor embedded isolation structure.

Abstract: A new method and structure is provided for the creation of a 1T-RAM cell. Shallow Trench Isolation (STI) regions are provided over a substrate. A 3D capacitor area is defined over the substrate, a patterned layer of polysilicon or HSG polysilicon is created aligned with the 3D capacitor area, providing the bottom plate of a 3D capacitor. Gate oxide is grown to form a dielectric for CMOS gate electrodes and the 3D capacitor dielectric. A patterned layer of polysilicon is created, defining gate electrodes and 3D capacitor upper plates.