Patents by Inventor Chung-Yi Yu

Chung-Yi Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9245991
    Abstract: A semiconductor device includes a substrate, a channel layer over the substrate, an active layer over the channel layer, and a barrier structure between the substrate and the channel layer. The active layer is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer. The barrier structure is configured to block diffusion of at least one of a material of the substrate or a dopant toward the channel layer.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: January 26, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Chun Liu, Chi-Ming Chen, Chen-Hao Chiang, Chung-Yi Yu, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 9233844
    Abstract: The present disclosure is directed to an integrated circuit and a method for the fabrication of the integrated circuit. The integrated circuit includes a lattice matching structure. The lattice matching structure can include a first buffer region, a second buffer region and a superlattice structure formed from AlxGa1-xN/AlyGa1-yN layer pairs.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: January 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Ming Chen, Po-Chun Liu, Chung-Yi Yu
  • Patent number: 9236464
    Abstract: A method of forming a high electron mobility transistor may include: forming a second III-V compound layer on a first III-V compound layer, the second III-V compound layer and the first III-V compound layer differing in composition; forming a p-type doped region in the first III-V compound layer; forming an n-type doped region in the second III-V compound layer, the n-type doped region overlying the p-type doped region; forming a source feature over the second III-V compound layer, the source feature overlying the n-type doped region; and forming a gate electrode over the second III-V compound layer, the gate electrode disposed laterally adjacent to the source feature.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: January 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hao Chiang, Chi-Ming Chen, Chung-Yi Yu, Po-Chun Liu, Han-Chin Chiu
  • Patent number: 9236465
    Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A diffusion barrier layer is disposed on top of the second III-V compound layer. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: January 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chun Liu, Chung-Yi Yu, Chi-Ming Chen
  • Patent number: 9224847
    Abstract: A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is greater than the first band gap. A crystalline interfacial layer is overlying and in contact with the second III-V compound layer. A gate dielectric is over the crystalline interfacial layer. A gate electrode is over the gate dielectric. A source region and a drain region are over the second III-V compound layer, and are on opposite sides of the gate electrode.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Chin Chiu, Po-Chun Liu, Chi-Ming Chen, Chung-Yi Yu, King-Yuen Wong
  • Publication number: 20150371994
    Abstract: Some embodiments of the present disclosure relate to a method for forming flash memory. In this method, a first tunnel oxide is formed over a semiconductor substrate. A self-assembled monolayer (SAM) is then formed on the first tunnel oxide. The SAM includes spherical or spherical-like crystalline silicon dots having respective diameters which are less than approximately 30 nm. A second tunnel oxide is then formed over the SAM.
    Type: Application
    Filed: June 19, 2014
    Publication date: December 24, 2015
    Inventors: Tsu-Hui Su, Chih-Ming Chen, Szu-Yu Wang, Chung-Yi Yu, Chia-Shiung Tsai
  • Patent number: 9209190
    Abstract: The present disclosure relates to a method of forming a capacitor structure, including depositing a plurality of first polysilicon (POLY) layers of uniform thickness separated by a plurality of oxide/nitride/oxide (ONO) layers over a bottom and sidewalls of a recess and substrate surface. A second POLY layer is deposited over the plurality of first POLY layers, is separated by an ONO layer, and fills a remainder of the recess. Portions of the second POLY layer and the second ONO layer are removed with a first chemical-mechanical polish (CMP). A portion of each of the plurality of first POLY layers and the first ONO layers on the surface which are not within a doped region of the capacitor structure are removed with a first pattern and etch process such that a top surface of each of the plurality of first POLY layers is exposed for contact formation.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: December 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Ming Chen, Szu-Yu Wang, Chung-Yi Yu
  • Publication number: 20150349106
    Abstract: A semiconductor structure includes a substrate; and a graded III-V layer over the substrate. The semiconductor structure further includes a p-doped gallium nitride (GaN) layer over the graded III-V layer. The semiconductor structure further includes one or more sets of GaN layers over the p-doped GaN layer. Each set of the one or more sets of GaN layers includes a lower GaN layer, wherein the lower GaN layer is undoped, unintentionally doped having N-type doping, or N-type doped. Each set of the one or more sets of GaN layers includes an upper GaN layer on the lower GaN layer, wherein the upper GaN layer is P-type doped. The semiconductor structure includes a second GaN layer over the one or more sets of GaN layers, the second GaN layer being either undoped or unintentionally doped having the N-type doping. The semiconductor structure includes an active layer over the second GaN layer.
    Type: Application
    Filed: August 12, 2015
    Publication date: December 3, 2015
    Inventors: Chi-Ming CHEN, Po-Chun LIU, Chung-Yi YU, Chia-Shiung TSAI
  • Patent number: 9202875
    Abstract: A method comprises depositing a first layer comprising aluminum nitride over a substrate. The method further comprises depositing a second layer comprising aluminum gallium nitride over the first layer. The method also comprises depositing a third layer comprising indium gallium nitride over the second layer. The method additionally comprises removing some of the third layer leaving a first portion of the third layer and a second portion of the third layer. The method further comprises reducing an aluminum content of at least the first layer by drawing aluminum atoms from the first layer into at least the second layer beneath the first portion and the second portion of the third layer. The method also comprises depositing a source contact over the first portion of the third layer and a drain contact over the second portion of the third layer.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: December 1, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hao Chiang, Po-Chun Liu, Chi-Ming Chen, Min-Chang Ching, Chung-Yi Yu, Chia-Shiung Tsai, Ru-Liang Lee
  • Publication number: 20150340473
    Abstract: A device includes insulation regions over portions of a semiconductor substrate, and a III-V compound semiconductor region over top surfaces of the insulation regions, wherein the III-V compound semiconductor region overlaps a region between opposite sidewalls of the insulation regions. The III-V compound semiconductor region includes a first and a second III-V compound semiconductor layer formed of a first III-V compound semiconductor material having a first band gap, and a third III-V compound semiconductor layer formed of a second III-V compound semiconductor material between the first and the second III-V compound semiconductor layers. The second III-V compound semiconductor material has a second band gap lower than the first band gap. A gate dielectric is formed on a sidewall and a top surface of the III-V compound semiconductor region. A gate electrode is formed over the gate dielectric.
    Type: Application
    Filed: July 31, 2015
    Publication date: November 26, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Ta Lin, Chun-Feng Nieh, Chung-Yi Yu, Chi-Ming Chen
  • Patent number: 9184041
    Abstract: Wafer bowing induced by deep trench capacitors is ameliorated by structures formed on the reverse side of the wafer. The structures on the reverse side include tensile films. The films can be formed within trenches on the back side of the wafer, which enhances their effect. In some embodiments, the wafers are used to form 3D-IC devices. In some embodiments, the 3D-IC device includes a high voltage or high power circuit.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: November 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Ming Chen, Szu-Yu Wang, Chung-Yi Yu
  • Publication number: 20150311300
    Abstract: Some embodiments of the present disclosure relate to a method for forming flash memory. In this method, a tunnel oxide is formed over a semiconductor substrate. A layer of silicon dot nucleates is formed on the tunnel oxide. The layer of silicon dots includes silicon dot nucleates having respective initial sizes which differ according to a first size distribution. An etching process is performed to reduce the initial sizes of the silicon dot nucleates so reduced-size silicon dot nucleates have respective reduced sizes which differ according to a second size distribution. The second size distribution has a smaller spread than the first size distribution.
    Type: Application
    Filed: April 25, 2014
    Publication date: October 29, 2015
    Inventors: Chih-Ming Chen, Tsu-Hui Su, Szu-Yu Wang, Chung-Yi Yu, Chia-Shiung Tsai, Ru-Liang Lee
  • Publication number: 20150287806
    Abstract: A method of making a semiconductor device includes epitaxially growing a channel layer over a substrate. The method further includes depositing an active layer over the channel layer. Additionally, the method includes forming a gate structure over the active layer, the gate structure configured to deplete a 2DEG under the gate structure, the gate structure including a dopant. Furthermore, the method includes forming a barrier layer between the gate structure and the active layer, the barrier layer configured to block diffusion of the dopant from the gate structure into the active layer.
    Type: Application
    Filed: June 22, 2015
    Publication date: October 8, 2015
    Inventors: Po-Chun LIU, Chi-Ming CHEN, Chen-Hao CHIANG, Chung-Yi YU, Chia-Shiung TSAI, Xiaomeng CHEN
  • Publication number: 20150287737
    Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of discrete storage elements within a memory cell. A copolymer solution having first and second polymer species is spin-coated onto a surface of a substrate and subjected to self-assembly into a phase-separated material having a regular pattern of micro-domains of the second polymer species within a polymer matrix having the first polymer species. The second polymer species is then removed resulting with a pattern of holes within the polymer matrix. An etch is then performed through the holes utilizing the polymer matrix as a hard-mask to form a substantially identical pattern of holes in a dielectric layer disposed over a seed layer disposed over the substrate surface. Epitaxial deposition onto the seed layer then utilized to grow a substantially uniform pattern of discrete storage elements within the dielectric layer.
    Type: Application
    Filed: June 22, 2015
    Publication date: October 8, 2015
    Inventors: Chih-Ming Chen, Tsung-Yu Chen, Cheng-Te Lee, Szu-Yu Wang, Chung-Yi Yu, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 9153435
    Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon (111) surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate. The high CTE layer has a CTE greater than the CTE of silicon. The method includes forming a buffer layer over the second side of the silicon substrate. The buffer layer has a CTE greater than the CTE of silicon. The method includes forming a III-V family layer over the buffer layer. The III-V family layer has a CTE greater than the CTE of the buffer layer.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: October 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Chen, Chung-Yi Yu, Chia-Shiung Tsai, Ho-Yung David Hwang
  • Patent number: 9142407
    Abstract: A semiconductor structure includes a substrate, a first III-V compound layer over the substrate, one or more sets of III-V compound layers over the first III-V compound layer, a second III-V compound layer over the one or more sets of III-V compound layers, and an active layer over the second III-V compound layer. The first III-V compound layer has a first type doping. Each of the one or more sets of III-V compound layers includes a lower III-V compound layer and an upper III-V compound layer over the lower III-V compound layer. The upper III-V compound layer having the first type doping, and the lower III-V compound layer is at least one of undoped, unintentionally doped having a second type doping, or doped having the second type doping. The second III-V compound layer is either undoped or unintentionally doped having the second type doping.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: September 22, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai
  • Patent number: 9123671
    Abstract: Provided is a method of fabricating a semiconductor device. The method includes: receiving a silicon wafer that contains oxygen; forming a zone in the silicon wafer, the zone being substantially depleted of oxygen; causing a nucleation process to take place in the silicon wafer to form oxygen nuclei in a region of the silicon wafer outside the zone; and growing the oxygen nuclei into defects. Also provided is an apparatus that includes a silicon wafer. The silicon wafer includes: a first portion that is substantially free of oxygen, the first portion being disposed near a surface of the silicon wafer; and a second portion that contains oxygen; wherein the second portion is at least partially surrounded by the first portion.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: September 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Chen, Chung-Yi Yu, Chia-Shiung Tsai, Ho-Yung David Hwang, Alexander Kalnitsky
  • Publication number: 20150236146
    Abstract: A high electron mobility transistor (HEMT) includes a substrate, and a channel layer over the substrate, wherein and at least one of the channel layer or the active layer comprises indium. The HEMT further includes an active layer over the channel layer. The active layer has a band gap discontinuity with the channel layer.
    Type: Application
    Filed: February 18, 2014
    Publication date: August 20, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Chun LIU, Chi-Ming CHEN, Min-Chang CHING, Chen-Hao CHIANG, Chung-Yi YU, Chung-Chieh HSU
  • Publication number: 20150236101
    Abstract: A method comprises depositing a first layer comprising aluminum nitride over a substrate. The method further comprises depositing a second layer comprising aluminum gallium nitride over the first layer. The method also comprises depositing a third layer comprising indium gallium nitride over the second layer. The method additionally comprises removing some of the third layer leaving a first portion of the third layer and a second portion of the third layer. The method further comprises reducing an aluminum content of at least the first layer by drawing aluminum atoms from the first layer into at least the second layer beneath the first portion and the second portion of the third layer. The method also comprises depositing a source contact over the first portion of the third layer and a drain contact over the second portion of the third layer.
    Type: Application
    Filed: February 18, 2014
    Publication date: August 20, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hao CHIANG, Po-Chun LIU, Chi-Ming CHEN, Min-Chang CHING, Chung-Yi YU, Chia-Shiung TSAI, Ru-Liang LEE
  • Patent number: 9099388
    Abstract: A device includes insulation regions over portions of a semiconductor substrate, and a III-V compound semiconductor region over top surfaces of the insulation regions, wherein the III-V compound semiconductor region overlaps a region between opposite sidewalls of the insulation regions. The III-V compound semiconductor region includes a first and a second III-V compound semiconductor layer formed of a first III-V compound semiconductor material having a first band gap, and a third III-V compound semiconductor layer formed of a second III-V compound semiconductor material between the first and the second III-V compound semiconductor layers. The second III-V compound semiconductor material has a second band gap lower than the first band gap. A gate dielectric is formed on a sidewall and a top surface of the III-V compound semiconductor region. A gate electrode is formed over the gate dielectric.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: August 4, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Ta Lin, Chun-Feng Nieh, Chung-Yi Yu, Chi-Ming Chen