Patents by Inventor Chung-Yi Yu

Chung-Yi Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10804101
    Abstract: A semiconductor structure including a substrate and a nucleation layer over the substrate. The semiconductor structure further includes a first III-V layer over the nucleation layer, wherein the first III-V layer includes a first dopant type. The semiconductor structure further includes one or more sets of III-V layers over the first III-V layer. Each set of the one or more sets of III-V layers includes a lower III-V layer, wherein the lower III-V layer has a second dopant type opposite the first dopant type, and an upper III-V layer on the lower III-V layer, wherein the upper III-V layer has the first dopant type. The semiconductor structure further includes a second III-V layer over the one or more sets of III-V layers, the second III-V layer having the second dopant type.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai
  • Patent number: 10777649
    Abstract: A quantum nano-tip (QNT) thin film, such as a silicon nano-tip (SiNT) thin film, for flash memory cells is provided to increase erase speed. The QNT thin film includes a first dielectric layer and a second dielectric layer arranged over the first dielectric layer. Further, the QNT thin film includes QNTs arranged over the first dielectric layer and extending into the second dielectric layer. A ratio of height to width of the QNTs is greater than 50 percent. A QNT based flash memory cell and a method for manufacture a SiNT based flash memory cell are also provided.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: September 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsu-Hui Su, Chih-Ming Chen, Chia-Shiung Tsai, Chung-Yi Yu, Szu-Yu Wang
  • Publication number: 20200131641
    Abstract: In some embodiments, a semiconductor fabrication tool is provided. The semiconductor fabrication tool includes a first processing zone having a first ambient environment and a second processing zone having a second ambient environment disposed at different location inside a processing chamber. A first exhaust port and a second exhaust port are disposed in the first and second processing zones, respectively. A first exhaust pipe couples the first exhaust port to a first individual exhaust output. A second exhaust pipe couples the second exhaust port to a second individual exhaust output, where the second exhaust pipe is separate from the first exhaust pipe. A first adjustable fluid control element controls the first ambient environment. A second adjustable fluid control element controls the second ambient environment, where the first adjustable fluid control element and the second adjustable fluid control element are independently adjustable.
    Type: Application
    Filed: March 13, 2019
    Publication date: April 30, 2020
    Inventors: Chiao-Chun Hsu, Chih-Ming Chen, Chung-Yi Yu, Sheng-Hsun Lu
  • Publication number: 20200083362
    Abstract: A semiconductor device includes a substrate. The semiconductor device includes an AlN seed layer in direct contact with the substrate. The AlN seed layer includes an AlN first seed sublayer, and an AlN second seed sublayer, wherein a portion of the AlN seed layer closest to the substrate includes carbon dopants and has a different lattice structure from a substrate lattice structure. The semiconductor device includes a graded layer in direct contact with the AlN seed layer. The graded layer includes a first graded sublayer including AlGaN, a second graded sublayer including AlGaN, and a third graded sublayer including AlGaN. The semiconductor device includes a channel layer over the graded layer. The semiconductor device includes an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer.
    Type: Application
    Filed: November 18, 2019
    Publication date: March 12, 2020
    Inventors: Chi-Ming CHEN, Po-Chun LIU, Chung-Yi YU, Chia-Shiung TSAI, Ru-Liang LEE
  • Publication number: 20200075314
    Abstract: Various embodiments of the present application are directed towards a group III-V device including a seed buffer layer that is doped and that is directly on a silicon substrate. In some embodiments, the group III-V device includes the silicon substrate, the seed buffer layer, a heterojunction structure, a pair of source/drain electrodes, and a gate electrode. The seed buffer layer overlies and directly contacts the silicon substrate. Further, the seed buffer layer includes a group III nitride (e.g., AlN) that is doped with p-type dopants. The heterojunction structure overlies the seed buffer layer. The source/drain electrodes overlie the heterojunction structure. The gate electrode overlies the heterojunction structure, laterally between the source/drain electrodes. The p-type dopants prevent the formation of a two-dimensional hole gas (2DHG) in the silicon substrate, along an interface at which the silicon substrate and the seed buffer layer directly contact.
    Type: Application
    Filed: April 26, 2019
    Publication date: March 5, 2020
    Inventors: Chi-Ming Chen, Chung-Yi Yu, Kuei-Ming Chen
  • Publication number: 20200058737
    Abstract: A silicon-on-insulator (SOI) substrate includes a semiconductor substrate and a multi-layered polycrystalline silicon structure. The multi-layered polycrystalline silicon structure is disposed over the semiconductor substrate. The multi-layered polycrystalline silicon structure includes a plurality of doped polycrystalline silicon layers stacked over one another, and an oxide layer between each adjacent pair of doped polycrystalline silicon layers. A number of the doped polycrystalline silicon layer is ranging from 2 to 6.
    Type: Application
    Filed: October 23, 2019
    Publication date: February 20, 2020
    Inventors: CHENG-TA WU, KUO-HWA TZENG, CHIH-HAO WANG, YEUR-LUEN TU, CHUNG-YI YU
  • Publication number: 20200035741
    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an epitaxial structure having a group IV chemical element disposed in a semiconductor substrate, where the epitaxial structure extends into the semiconductor substrate from a first side of the semiconductor substrate. A photodetector is at least partially arranged in the epitaxial structure. A first capping structure having a first capping structure chemical element that is different than the first group IV chemical element covers the epitaxial structure on the first side of the semiconductor substrate. A second capping structure is arranged between the first capping structure and the epitaxial structure, where the second capping structure includes the group IV chemical element and the first capping structure chemical element.
    Type: Application
    Filed: July 27, 2018
    Publication date: January 30, 2020
    Inventors: Po-Chun Liu, Chung-Yi Yu, Eugene Chen
  • Publication number: 20200028070
    Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 23, 2020
    Inventors: Chih-Ming Chen, Chern-Yow Hsu, Szu-Yu Wang, Chung-Yi Yu, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20200020845
    Abstract: A device includes a substrate, a first layer of getter material, a first electrode, an insulator element, a second electrode, a first input-output electrode, and a second input-output electrode. The first layer of getter material is deposited on the substrate. The first electrode is formed in a first conductive layer deposited on the first layer of getter material. The first layer of getter material has a getter capacity for hydrogen that is higher than the first electrode. The insulator element is formed in a piezoelectric layer deposited on the first electrode. The second electrode is formed in a second conductive layer deposited on the insulator element. The first input-output electrode is conductively connecting to the first layer of getter material. The second input-output electrode is conductively connecting to the second electrode.
    Type: Application
    Filed: August 22, 2018
    Publication date: January 16, 2020
    Inventors: Chih-Ming Chen, Chung-Yi Yu
  • Patent number: 10497560
    Abstract: Some embodiments of the present disclosure relate to a method for forming flash memory. In this method, a tunnel oxide is formed over a semiconductor substrate. A layer of silicon dot nucleates is formed on the tunnel oxide. The layer of silicon dots includes silicon dot nucleates having respective initial sizes which differ according to a first size distribution. An etching process is performed to reduce the initial sizes of the silicon dot nucleates so reduced-size silicon dot nucleates have respective reduced sizes which differ according to a second size distribution. The second size distribution has a smaller spread than the first size distribution.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: December 3, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Ming Chen, Tsu-Hui Su, Szu-Yu Wang, Chung-Yi Yu, Chia-Shiung Tsai, Ru-Liang Lee
  • Patent number: 10497860
    Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: December 3, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Ming Chen, Chern-Yow Hsu, Szu-Yu Wang, Chung-Yi Yu, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 10483386
    Abstract: A semiconductor device includes a substrate, and a seed layer over the substrate, wherein the seed layer comprises carbon dopants. The semiconductor device further includes a channel layer over the seed layer, and an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer. A method of making a transistor includes forming a seed layer over a substrate, and doping the seed layer, wherein doping the seed layer comprises introducing carbon dopants into the seed layer. The method further includes forming a channel layer over the seed layer, and forming an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: November 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai, Ru-Liang Lee
  • Patent number: 10468486
    Abstract: A silicon-on-insulator (SOI) substrate includes a semiconductor substrate and a multi-layered polycrystalline silicon structure. The multi-layered polycrystalline silicon structure is disposed over the semiconductor substrate. The multi-layered polycrystalline silicon structure includes a plurality of polycrystalline silicon layers stacked over one another, and a native oxide layer between each adjacent pair of polycrystalline silicon layers.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: November 5, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheng-Ta Wu, Kuo-Hwa Tzeng, Chih-Hao Wang, Yeur-Luen Tu, Chung-Yi Yu
  • Publication number: 20190305122
    Abstract: The semiconductor structure includes a p-type doped III-V compound layer, a III-V compound channel layer over the p-type doped III-V compound layer, and a barrier layer. The III-V compound channel layer includes an upper region and a lower region, and the barrier layer is sandwiched between the upper region and the lower region of the III-V channel compound layer. The III-V compound channel layer includes a first band gap, the barrier layer includes a second band gap, and the second band gap is greater than the first band gap.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Inventors: CHI-MING CHEN, KUEI-MING CHEN, CHUNG-YI YU
  • Publication number: 20190241430
    Abstract: A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis.
    Type: Application
    Filed: April 15, 2019
    Publication date: August 8, 2019
    Inventors: Hung-Hua Lin, Chang-Ming Wu, Chung-Yi Yu, Ping-Yin Liu, Jung-Huei Peng
  • Publication number: 20190244914
    Abstract: Some embodiments relate to a method. In this method, a semiconductor wafer having a frontside and a backside is received. A frontside structure is formed on the frontside of the semiconductor wafer. The frontside structure exerts a first wafer-bowing stress that bows the semiconductor wafer by a first bow amount. A characteristic is determined for one or more stress-inducing films to be formed based on the first bow amount. The one or more stress-inducing films are formed with the determined characteristic on the backside of the semiconductor wafer and/or on the frontside of the semiconductor wafer to reduce the first bow amount in the semiconductor wafer.
    Type: Application
    Filed: April 17, 2019
    Publication date: August 8, 2019
    Inventors: Chih-Ming Chen, Szu-Yu Wang, Chung-Yi Yu
  • Patent number: 10351418
    Abstract: An embodiment method includes forming a first plurality of bond pads on a device substrate, depositing a spacer layer over and extending along sidewalls of the first plurality of bond pads, and etching the spacer layer to remove lateral portions of the spacer layer and form spacers on sidewalls of the first plurality of bond pads. The method further includes bonding a cap substrate including a second plurality of bond pads to the device substrate by bonding the first plurality of bond pads to the second plurality of bond pads.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Ming Chen, Ping-Yin Liu, Chung-Yi Yu, Yeur-Luen Tu
  • Patent number: 10294098
    Abstract: A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Hua Lin, Chang-Ming Wu, Chung-Yi Yu, Ping-Yin Liu, Jung-Huei Peng
  • Publication number: 20190131416
    Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.
    Type: Application
    Filed: December 24, 2018
    Publication date: May 2, 2019
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Chung-Yi Yu, Chen-Hao Chiang
  • Publication number: 20190131400
    Abstract: A silicon-on-insulator (SOI) substrate includes a semiconductor substrate and a multi-layered polycrystalline silicon structure. The multi-layered polycrystalline silicon structure is disposed over the semiconductor substrate. The multi-layered polycrystalline silicon structure includes a plurality of polycrystalline silicon layers stacked over one another, and a native oxide layer between each adjacent pair of polycrystalline silicon layers.
    Type: Application
    Filed: January 3, 2018
    Publication date: May 2, 2019
    Inventors: CHENG-TA WU, KUO-HWA TZENG, CHIH-HAO WANG, YEUR-LUEN TU, CHUNG-YI YU