Patents by Inventor Chung-Zen Chen
Chung-Zen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150269975Abstract: An exemplary embodiment of the present disclosure provides a programming voltage generator for a nonvolatile memory device. The programming voltage generator comprises a power circuit, a detector, a switching circuit, a control signal generator, and a regulation circuit. The power circuit outputs a programming voltage according to a voltage control signal. The detector detects whether the programming voltage is larger than or equal to a breakdown voltage of the nonvolatile memory device, so as to output an indication signal. The switching circuit temporally drops the programming voltage according to the indication signal. The control signal generator generates a plurality of regulation control signals. The regulation circuit generates the voltage control signal according to the programming signal and the regulation control signals.Type: ApplicationFiled: March 21, 2014Publication date: September 24, 2015Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.Inventor: CHUNG-ZEN CHEN
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Patent number: 9047977Abstract: A circuit for outputting a refresh execution signal to a memory cell of a memory device in an auto-refresh mode comprises a first frequency dividing unit, a first selection circuit, a second frequency dividing unit, and a second selection circuit. The first frequency dividing unit receives an auto-refresh signal from outside the memory device and generates a plurality of first divided signals. The first selection circuit generates a selection signal selected from the auto-refresh signal and the first divided signals. The second frequency dividing unit divides the frequency of the selection signal and generates a plurality of second divided signals. The second selection circuit generates the refresh execution signal from the selection signal and the second divided signals.Type: GrantFiled: May 11, 2011Date of Patent: June 2, 2015Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Chung Zen Chen
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Patent number: 8913442Abstract: A circuit for sensing a multi-level cell (MLC) flash memory is disclosed. The circuit comprises a plurality of first decoding units, a second decoding unit and a data latch. Each of the first decoding units provides a timing information and includes a controlled transistor to allow a current to pass therethrough, and a capacitor to be charged by the current or to discharge through the controlled transistor. The second decoding unit provides a latch signal and includes a controlled transistor to allow a current to pass therethrough, the magnitude of the current being associated with data in an MLC, and a capacitor to be charged by the current or to discharge through the controlled transistor. The data latch, in response to the timing information from each of the first decoding units and the latch signal from the second decoding unit, determines the data in the MLC.Type: GrantFiled: December 21, 2012Date of Patent: December 16, 2014Assignee: Elite Semiconductor Memory Technology Inc.Inventors: Chung Zen Chen, Yi Shin Huang
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Patent number: 8649236Abstract: A circuit for controlling leakage current in random access memory devices comprises a pre-charge equalization circuit. The pre-charge equalization circuit provides a pre-charge voltage to a pair of complementary bit lines of a memory cell of a random access memory device in accordance with a pre-charge signal. When the memory cell is in a self-refresh mode, the pre-charge signal is activated by a periodically triggered pre-charge request and also activated before and after the memory cell is self-refreshed.Type: GrantFiled: May 11, 2011Date of Patent: February 11, 2014Assignee: Elite Semiconductor Memory Technology Inc.Inventors: Chung Zen Chen, Ying Wei Jan, Jian Shiang Liang
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Patent number: 8581560Abstract: A voltage regulator circuit comprises active and standby amplifiers, first and second transistors, and a capacitor. The active amplifier has a negative input connected to a first reference voltage, and the standby amplifier has a negative input connected to a second reference voltage. The first reference voltage is greater than the second reference voltage. The first transistor has a gate connected to an output of the active amplifier and a drain connected to a voltage regulated output, and the second transistor has a gate connected to an output of the standby amplifier and a drain connected to the voltage regulated output. The capacitor is connected between a chip enable signal and the voltage regulated output.Type: GrantFiled: July 1, 2010Date of Patent: November 12, 2013Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Chung-Zen Chen
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Patent number: 8565040Abstract: A voltage regulator circuit for providing power management for a memory device is disclosed. The voltage regulator circuit comprises a voltage regulator and a switch circuit. The switch circuit includes a first oscillator to generate an oscillating signal, and a pulse generator to generate a pulse signal in response to the oscillating signal. The voltage regulator provides a current during standby mode of the memory device in response to the pulse signal. The current is smaller than one provided by the voltage regulator during normal mode of the memory device.Type: GrantFiled: May 17, 2012Date of Patent: October 22, 2013Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Chung Zen Chen
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Publication number: 20130250695Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.Type: ApplicationFiled: May 16, 2013Publication date: September 26, 2013Applicant: Mosaid Technologies IncorporatedInventors: Chung-Zen Chen, Yang-Chieh Lin, Chung-Shan Kuo
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Patent number: 8456922Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.Type: GrantFiled: May 22, 2012Date of Patent: June 4, 2013Assignee: MOSAID Technologies IncorporatedInventors: Chung-Zen Chen, Yang-Chieh Lin, Chung-Shan Kuo
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Patent number: 8405375Abstract: A circuit for providing a reference voltage includes a bandgap reference circuit, a first unity gain buffer coupled to the bandgap reference circuit, a first switch for coupling a second reference voltage node to a third reference voltage node, a first capacitor coupled to the third reference voltage node, a second switch for coupling the third reference voltage node to a fourth reference voltage node, and a second capacitor coupled to the fourth reference voltage node, wherein during operation a fourth reference voltage at the fourth reference voltage node decays when the second capacitor discharges. A control circuit provides control signals for intermittently operating the bandgap reference circuit and for controlling the switches to recharge the second capacitor after the fourth reference voltage decays a predetermined amount.Type: GrantFiled: June 24, 2011Date of Patent: March 26, 2013Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Chung-Zen Chen
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Patent number: 8406067Abstract: The present invention provides a semiconductor memory device, the voltage divider circuit comprises a data line sense amplifier and an input output data sensing circuit. The data line sense amplifier receives a data line signal pair and senses the data line signal pair in a first timing period to generate a first output data and a second output data, wherein, the first output data and the second output data are complementary. The input output data sensing circuit receives at least one reference output data and one of the first and the second output data. The input output data sensing circuit generates a sensed data by comparing voltage levels of the reference output data and the one of the first and the second output data in a second timing period, wherein the voltage level of the reference output data is a pre-determined voltage level.Type: GrantFiled: July 21, 2011Date of Patent: March 26, 2013Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Chung-Zen Chen
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Patent number: 8391092Abstract: A method for eliminating bit line leakage current of a memory cell in random access memory devices comprises the steps of: periodically activating a pre-charge equalization circuit, which provides a pre-charge voltage to a pair of complementary bit lines of a memory cell, if the memory cell is in a self-refresh mode or a standby mode; and temporarily activating the pre-charge equalization circuit after the memory cell is refreshed if the memory cell is in the self-refresh mode or the standby mode.Type: GrantFiled: July 2, 2010Date of Patent: March 5, 2013Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Chung Zen Chen
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Patent number: 8369170Abstract: A method for determining a temperature in a circuit comprises receiving a periodic signal. A frequency of the periodic signal is an increasing function of temperature. A number of oscillations of the periodic signal is determined during a time interval. A length of the time interval is an increasing function of temperature. The temperature is based on the determined number of oscillations.Type: GrantFiled: March 22, 2011Date of Patent: February 5, 2013Assignee: MOSAID Technologies IncorporatedInventor: Chung Zen Chen
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Publication number: 20130021855Abstract: The present invention provides a semiconductor memory device, the voltage divider circuit comprises a data line sense amplifier and an input output data sensing circuit. The data line sense amplifier receives a data line signal pair and senses the data line signal pair in a first timing period to generate a first output data and a second output data, wherein, the first output data and the second output data are complementary. The input output data sensing circuit receives at least one reference output data and one of the first and the second output data. The input output data sensing circuit generates a sensed data by comparing voltage levels of the reference output data and the one of the first and the second output data in a second timing period, wherein the voltage level of the reference output data is a pre-determined voltage level.Type: ApplicationFiled: July 21, 2011Publication date: January 24, 2013Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.Inventor: Chung-Zen Chen
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Publication number: 20120326695Abstract: A circuit for providing a reference voltage includes a bandgap reference circuit, a first unity gain buffer coupled to the bandgap reference circuit, a first switch for coupling a second reference voltage node to a third reference voltage node, a first capacitor coupled to the third reference voltage node, a second switch for coupling the third reference voltage node to a fourth reference voltage node, and a second capacitor coupled to the fourth reference voltage node, wherein during operation a fourth reference voltage at the fourth reference voltage node decays when the second capacitor discharges. A control circuit provides control signals for intermittently operating the bandgap reference circuit and for controlling the switches to recharge the second capacitor after the fourth reference voltage decays a predetermined amount.Type: ApplicationFiled: June 24, 2011Publication date: December 27, 2012Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.Inventor: Chung-Zen Chen
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Publication number: 20120287739Abstract: A circuit for controlling leakage current in random access memory devices comprises a pre-charge equalization circuit. The pre-charge equalization circuit provides a pre-charge voltage to a pair of complementary bit lines of a memory cell of a random access memory device in accordance with a pre-charge signal. When the memory cell is in a self-refresh mode, the pre-charge signal is activated by a periodically triggered pre-charge request and also activated before and after the memory cell is self-refreshed.Type: ApplicationFiled: May 11, 2011Publication date: November 15, 2012Applicant: Elite Semiconductor Memory Technology Inc.Inventors: Chung Zen Chen, Ying Wei Jan, Jian Shiang Liang
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Publication number: 20120287742Abstract: A circuit for outputting a refresh execution signal to a memory cell of a memory device in an auto-refresh mode comprises a first frequency dividing unit, a first selection circuit, a second frequency dividing unit, and a second selection circuit. The first frequency dividing unit receives an auto-refresh signal from outside the memory device and generates a plurality of first divided signals. The first selection circuit generates a selection signal selected from the auto-refresh signal and the first divided signals. The second frequency dividing unit divides the frequency of the selection signal and generates a plurality of second divided signals. The second selection circuit generates the refresh execution signal from the selection signal and the second divided signals.Type: ApplicationFiled: May 11, 2011Publication date: November 15, 2012Applicant: Elite Semiconductor Memory Technology Inc.Inventor: Chung Zen CHEN
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Publication number: 20120230119Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.Type: ApplicationFiled: May 22, 2012Publication date: September 13, 2012Applicant: MOSAID Technologies IncorporatedInventors: Chung-Zen Chen, Yang-Chieh Lin, Chung-Shan Kuo
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Patent number: 8199593Abstract: A method for controlling standby current coming from bit line leakage in random access memory devices comprises the steps of: continuously deactivating a pre-charge equalization circuit providing a pre-charge voltage to a pair of complementary bit lines of a memory cell if the memory cell is in a self-refresh mode, a standby mode or an active mode; temporarily activating the pre-charge equalization circuit before the memory cell is refreshed if the memory cell is in a self-refresh mode or a standby mode; and temporarily activating the pre-charge equalization circuit before the memory cell is refreshed or accessed if the memory cell is in an active mode.Type: GrantFiled: July 2, 2010Date of Patent: June 12, 2012Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Chung Zen Chen
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Patent number: 8194491Abstract: A power-up circuit comprises an external supply voltage potential detector, a first internal supply voltage potential detector, a second internal supply voltage potential detector, and a logic circuit. The external supply voltage potential detector is configured to detect a supply voltage that is external to the memory device and to generate a first detection signal indicating whether a voltage potential of the external supply voltage reaches a first predetermined value. The first internal supply voltage potential detector is configured to detect a first internal supply voltage that is internal to the memory device and to generate a second detection signal indicating whether a voltage potential of the first internal supply voltage reaches a second predetermined value.Type: GrantFiled: March 22, 2010Date of Patent: June 5, 2012Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Chung Zen Chen
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Patent number: 8189396Abstract: A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.Type: GrantFiled: December 14, 2006Date of Patent: May 29, 2012Assignee: Mosaid Technologies IncorporatedInventors: Chung-Zen Chen, Yang-Chieh Lin, Chung-Shan Kuo