Abstract: A method of biasing word lines in a flash memory array wherein a selected word line is selected for a reading operation during data access includes the steps of biasing deselected word lines with a deselected word line voltage, delaying for a delay period and after the delay period, biasing the selected word line with a selected word line voltage for performing the reading operation.

Abstract: Methods for programming and reading a multi-level-cell NAND flash memory device having plural memory cells are disclosed to reduce the programming time and the reading time. The program method comprises the steps of: (a) programming the zero state memory cells, the first state memory cells, the second state memory cells and the third state memory cells to a zero state, (b) programming the second state memory cells from the zero state to a second state by switching the MSBs of the second state memory cells, and (c) programming the first state memory cells from the zero state to a first state by switching the LSBs of the first state memory cells and simultaneously programming the third state memory cells from the second state to a third state by switching the LSBs of the third state memory cells.

Abstract: A method for reading a NAND flash memory device having plural normal cells, which utilizes plural reference bit lines associated with plural reference cells to read the normal cells in one phase to reduce the read time, is disclosed. The method comprises ramping up a selected word line voltage in a predetermined period and reading the normal cells with a zero state, a first state, a second state and a third state in the predetermined period. The present invention also discloses a memory cell array concerning the method for reading a NAND flash memory device.

Abstract: A non-volatile memory device with a page buffer having dual registers includes a memory cell array, a selector circuit and a page buffer circuit, the selector circuit being coupled to an exterior data line, the page buffer circuit including a first register and a second register being coupled between the memory cell array and the selector circuit, and the first register and second register being commonly coupled through a sense node. The first and second registers alternately write data to the memory cell array for programming. As one of the first and second registers performs programming, the other register stores data from the data line concurrently. In other words, the second register stores data from the data line when the first register is in programming, whereas the first register stores data from the data line when the second register is in programming.

Abstract: A charge pump circuit including a plurality of controlled charge pumps (CPs), a plurality of uncontrolled CPs, a plurality of control units, and an output unit is provided. Each controlled CP determines whether to provide charges to a node by a control signal, and each uncontrolled CP constantly provides charges to the node. The higher the node voltage at the node is, the more the controlled CPs not providing charge to the node are, so as to suppress the voltage of the node. In addition, the output unit regulates and outputs an output voltage according to the node voltage by the negative feedback.

Abstract: Methods for programming and reading a multi-level-cell NAND flash memory device having plural memory cells are disclosed to reduce the programming time and the reading time. The program method comprises the steps of: (a) programming the zero state memory cells, the first state memory cells, the second state memory cells and the third state memory cells to a zero state, (b) programming the second state memory cells from the zero state to a second state by switching the MSBs of the second state memory cells, and (c) programming the first state memory cells from the zero state to a first state by switching the LSBs of the first state memory cells and simultaneously programming the third state memory cells from the second state to a third state by switching the LSBs of the third state memory cells.

Abstract: A method for preventing the over-erase in a nonvolatile memory comprises the following steps. First, at least one normal cell of the nonvolatile memory and at least one reference cell that corresponds to the at least one normal cell are provided with a constant current. Second, the erasing threshold voltage of the at least one normal cell is determined, and then the at least one normal cell is erased to be of the erasing threshold voltage. By virtue of adding the constant current, the higher erasing threshold voltage can be acquired, and in consequence over-erase can be avoided.

Abstract: A NAND non-volatile two-bit memory cell comprises a cell stack and two select stacks disposed on an active area of a substrate. Each select stack is respectively disposed on a side of the cell stack with a sidewall between the cell stack and a respective select stack. The cell stack has four components: a first dielectric layer disposed over the substrate; a charge accumulation layer capable of holding charge in a portion thereof to store information and disposed over the first dielectric layer; a second dielectric layer disposed over the charge accumulation layer; and a control gate disposed over the second dielectric layer. The select stack has two components: a third dielectric layer disposed over the substrate and a select gate, capable of inverting an underneath channel region to function as a source or a drain of the memory cell, disposed over the third dielectric layer.

Abstract: An erase method used in an array of flash memory cells arranged in a plurality of sectors provides each sector with an erase flag. The erase flag of sectors to be erased are set to a first value. The memory cells are sequentially verified from a first sector to a last sector whose flag is set to the first value and for each sector from a first address to a last address. When verification fails and the number of the same-cell-verifications is less than a predetermined number, the method applies an erase pulse and verifies the memory call at the same memory address again. When verification fails and the number of same-cell-verifications reaches the predetermined number, the remaining sectors whose flag is set to the first value are verified. When each memory cell of a sector to be erased passes verification, the erase flag of the sector is set to a second value. When the flag of each sector to be erased is set to the second value, the erase operation is terminated.

Abstract: A method of automatically determining a sensing timing in a page buffer of a NAND flash memory device is disclosed, which includes the steps of discharging a first reference bit line, discharging a second reference bit line, determining a first control signal and determining a second control signal. To perform the method, an apparatus of automatically determining a sensing timing in a page buffer of a NAND flash memory device is also disclosed. The apparatus includes a first reference bit line, a first current sink, a first reference page buffer, the second reference bit line, a second current sink and a second reference page buffer. The first reference bit line is coupled to the first current sink and the first reference page buffer at both ends thereof. The second reference bit line is coupled to the second current sink and the second reference page buffer at both ends thereof.

Abstract: In a method of erasing flash memory cells, the flash memory cells organized in selectable memory blocks, the erasing step comprising applying an erase pulse voltage to a commonly biased cell well of at least one selected and at least one unselected memory blocks, the method comprising the steps of: raising the erase pulse voltage to a first intermediate voltage less than a target erase pulse voltage; maintaining the erase pulse voltage at the first intermediate voltage for a first period of time; after the first time period, raising the erase pulse voltage to the target erase pulse voltage; and maintaining the erase pulse voltage at the target erase pulse voltage during an erase operation.

Abstract: A method of biasing word lines in a flash memory array wherein a selected word line is selected for a reading operation during data access includes the steps of biasing deselected word lines with a deselected word line voltage, delaying for a delay period and after the delay period, biasing the selected word line with a selected word line voltage for performing the reading operation.

Abstract: An erase method used in an array of flash memory cells arranged in a plurality of sectors provides each sector with an erase flag. The erase flag of sectors to be erased are set to a first value. The memory cells are sequentially verified from a first sector to a last sector whose flag is set to the first value and for each sector from a first address to a last address. When verification fails and the number of the same-cell-verifications is less than a predetermined number, the method applies an erase pulse and verifies the memory call at the same memory address again. When verification fails and the number of same-cell-verifications reaches the predetermined number, the remaining sectors whose flag is set to the first value are verified. When each memory cell of a sector to be erased passes verification, the erase flag of the sector is set to a second value. When the flag of each sector to be erased is set to the second value, the erase operation is terminated.

Abstract: A nonvolatile memory comprises a plurality of memory cells, a bit line control circuit and a verifying circuit. The bit line control circuit includes a driving circuit and a non-driving circuit. The verifying circuit verifies a first threshold voltage of the memory cell when the driving circuit drives the memory cell. The verifying circuit also verifies a second threshold voltage when the driving circuit does not drive the memory cell.

Abstract: A nonvolatile memory comprises a plurality of memory cells, a bit line control circuit and a verifying circuit. The bit line control circuit includes a driving circuit and a non-driving circuit. The verifying circuit verifies a first threshold voltage of the memory cell when the driving circuit drives the memory cell. The verifying circuit also verifies a second threshold voltage when the driving circuit does not drive the memory cell.

Abstract: A method of overerase correction for memory cells in a memory array after the memory cells have been erased is provided comprising the following steps: (a) setting a gate voltage of memory cells from a first selected bit line exhibiting leakage current above a threshold value to an initial voltage level; (b) applying a series of overerase correction pulses to the first selected bit line during a selected time period; (c) detecting during the selected time period whether the bit line exhibits leakage current above the threshold value; (d) if the bit line exhibits leakage current above the threshold value after the selected time period, increasing the gate voltage and repeating steps (b) and (c); and (e) if it is detected that the bit line does not exhibit leakage current above the threshold value during the selected time period, selecting a second bit line and repeating steps (a) through (d).

Abstract: A method is provided of regulating a supply voltage for providing a bit line voltage in a semiconductor memory device where the bit line voltage is provided to memory cells in a bit line from the supply voltage through a bit switch. A bit line current provided to the memory cells is detected. The supply voltage is adjusted responsive to the deducted bit line current to at least partially compensate for a voltage drop across the bit switch where the voltage drop is dependent at least in part on the bit line current.

Abstract: A method for preventing the over-erase in a nonvolatile memory comprises the following steps. First, at least one normal cell of the nonvolatile memory and at least one reference cell that corresponds to the at least one normal cell are provided with a constant current. Second, the erasing threshold voltage of the at least one normal cell is determined, and then the at least one normal cell is erased to be of the erasing threshold voltage. By virtue of adding the constant current, the higher erasing threshold voltage can be acquired, and in consequence over-erase can be avoided.

Abstract: A memory comprising a memory array, a plurality of word lines, a plurality of bit lines, a word line decoder, an equalizer and an equalization control apparatus is provided to meet the requirement of the completion of bit line equalization prior to the turn on of word lines. The memory array is arranged in columns and rows. The word lines are connected to the rows of the memory array. The bit lines connected to the columns of the memory array. The word line decoder is connected to the word lines for selecting one of the word lines. The equalizer is connected to the bit lines for equalizing the bit lines to a desired voltage. The equalization control apparatus serves for monitoring the equalizer to disable the word line decoder when the equalizer performs a equalization operation and enable the word line decoder when the equalization operation is completed.

Abstract: A memory comprising a memory array, a plurality of word lines, a plurality of bit lines, a word line decoder, an equalizer and an equalization control apparatus is provided to meet the requirement of the completion of bit line equalization prior to the turn on of word lines. The memory array is arranged in columns and rows. The word lines are connected to the rows of the memory array. The bit lines connected to the columns of the memory array. The word line decoder is connected to the word lines for selecting one of the word lines. The equalizer is connected to the bit lines for equalizing the bit lines to a desired voltage. The equalization control apparatus serves for monitoring the equalizer to disable the word line decoder when the equalizer performs a equalization operation and enable the word line decoder when the equalization operation is completed.