Patents by Inventor Chung-Zen Chen
Chung-Zen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8106692Abstract: A method for tracking a delay locked loop (DLL) clock is described. An external clock signal is allowed to pass through delay cells of a DLL during a first period of the external clock signal when a transition edge of a track signal applied on the DLL occurs. Then, when a transition edge of a sensing signal applied on the DLL occurs at a start of a second period of the external clock signal, the external clock signal is inhibited to pass through the delay cells and the number of the delay cells through which the external signal pass during the first period of the external clock signal is counted. When a reset signal is asserted, a delay time of each delay cell is reset such that a ratio of the delay time to the period of the external clock signal is kept from 10% to 15%.Type: GrantFiled: March 3, 2010Date of Patent: January 31, 2012Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Chung-Zen Chen
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Patent number: 8107315Abstract: A double data rate memory device comprises first and second sense amplifiers, a data selection circuit, and a data processing circuit. The first sense amplifier is configured to provide even data loaded on a first input and output data line, and the second sense amplifier is configured to provide odd data loaded on a second input and output data line. The data selection circuit is connected to the first and second sense amplifiers and is configured to provide output data loaded on a single data line, and the data processing circuit connected to the data selection circuit and configured to transfer the even data and the odd data in first and second data paths. The even data and the odd data are combined into the output data of the data selection circuit, and the data selection circuit selects the output data in response to a least significant bit of a column address and transfers the selected data on the single data line in response to a clock signal.Type: GrantFiled: March 22, 2010Date of Patent: January 31, 2012Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Chung Zen Chen
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Publication number: 20120001606Abstract: A voltage regulator circuit comprises active and standby amplifiers, first and second transistors, and a capacitor. The active amplifier has a negative input connected to a first reference voltage, and the standby amplifier has a negative input connected to a second reference voltage. The first reference voltage is greater than the second reference voltage. The first transistor has a gate connected to an output of the active amplifier and a drain connected to a voltage regulated output, and the second transistor has a gate connected to an output of the standby amplifier and a drain connected to the voltage regulated output. The capacitor is connected between a chip enable signal and the voltage regulated output.Type: ApplicationFiled: July 1, 2010Publication date: January 5, 2012Inventor: Chung-Zen Chen
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Publication number: 20120002496Abstract: A method for eliminating bit line leakage current of a memory cell in random access memory devices comprises the steps of: periodically activating a pre-charge equalization circuit, which provides a pre-charge voltage to a pair of complementary bit lines of a memory cell, if the memory cell is in a self-refresh mode or a standby mode; and temporarily activating the pre-charge equalization circuit after the memory cell is refreshed if the memory cell is in the self-refresh mode or the standby mode.Type: ApplicationFiled: July 2, 2010Publication date: January 5, 2012Inventor: Chung Zen Chen
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Publication number: 20120002497Abstract: A method for controlling standby current coming from bit line leakage in random access memory devices comprises the steps of: continuously deactivating a pre-charge equalization circuit providing a pre-charge voltage to a pair of complementary bit lines of a memory cell if the memory cell is in a self-refresh mode, a standby mode or an active mode; temporarily activating the pre-charge equalization circuit before the memory cell is refreshed if the memory cell is in a self-refresh mode or a standby mode; and temporarily activating the pre-charge equalization circuit before the memory cell is refreshed or accessed if the memory cell is in an active mode.Type: ApplicationFiled: July 2, 2010Publication date: January 5, 2012Inventor: Chung Zen Chen
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Publication number: 20120001231Abstract: An electrical fuse comprises first, second, and third thick oxide NMOS transistors and a thin oxide NMOS transistor. The first thick oxide NMOS transistor has a gate connected to a first input signal, and the thin oxide NMOS transistor has a drain connected to the source of the first thick oxide NMOS transistor and a gate shorted to its source. The second thick oxide transistor has a gate connected to a power up signal, a drain connected to the source of the thin oxide NMOS transistor, and a source connected to a reference voltage. The third thick oxide transistor has a gate connected to the second input signal, a drain connected to a high voltage, and a source connected to the drain of the thin oxide NMOS transistor. The first input signal and the second input signal are complementary.Type: ApplicationFiled: June 30, 2010Publication date: January 5, 2012Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.Inventor: Chung Zen Chen
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Patent number: 8081520Abstract: An over erase correction method of a flash memory apparatus is provided. The flash memory apparatus includes at least a microprocessor, a memory array, a bit line exchange unit and a column decoder. By controlling the column decoder of the flash memory during a period of the over-erase correction, the column decoder outputs control signals to the bit line exchange unit for selecting at least one of the bit lines according to a magnitude of the bit line leakage current. The drop in the charge pump voltage due to the bit line leakage current is reduced, and thus, the over-erase correction is executed effectively during the period of the over-erase correction.Type: GrantFiled: February 3, 2010Date of Patent: December 20, 2011Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Chung-Zen Chen
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Patent number: 8045374Abstract: A suitable erase verification (ERSV) method of a flash memory apparatus is provided, which is different from the conventional ERSV method. That is, by managing the ERSV operation on the flash memory after at least once of erase operation, a flash memory controller in the flash memory apparatus selectively assigns at least one of de-selected sectors instead of all of the de-selected sectors to perform the ERSV. Therefore, by managing the ERSV operation on the flash memory, the time for the ERSV operation thereon is reduced.Type: GrantFiled: January 19, 2010Date of Patent: October 25, 2011Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Chung-Zen Chen
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Patent number: 8031550Abstract: A voltage regulator circuit for a memory circuit comprises a voltage divider, a capacitor, an active-mode voltage regulator and a standby-mode voltage regulator. The active-mode voltage regulator is always on while in active mode, and turned on whenever a refresh is requested. The standby-mode voltage regulator is periodically turned on while in standby mode, and turned on whenever a refresh is requested. In addition, the active voltage regulator uses stronger transistors than those used by the standby-mode voltage regulator, and both the active-mode voltage regulator and the standby-mode voltage regulator are coupled to the voltage divider and the capacitor.Type: GrantFiled: June 3, 2008Date of Patent: October 4, 2011Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Chung Zen Chen
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Publication number: 20110228623Abstract: A power-up circuit comprises an external supply voltage potential detector, a first internal supply voltage potential detector, a second internal supply voltage potential detector, and a logic circuit. The external supply voltage potential detector is configured to detect a supply voltage that is external to the memory device and to generate a first detection signal indicating whether a voltage potential of the external supply voltage reaches a first predetermined value. The first internal supply voltage potential detector is configured to detect a first internal supply voltage that is internal to the memory device and to generate a second detection signal indicating whether a voltage potential of the first internal supply voltage reaches a second predetermined value.Type: ApplicationFiled: March 22, 2010Publication date: September 22, 2011Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.Inventor: CHUNG ZEN CHEN
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Publication number: 20110228627Abstract: A double data rate memory device comprises first and second sense amplifiers, a data selection circuit, and a data processing circuit. The first sense amplifier is configured to provide even data loaded on a first input and output data line, and the second sense amplifier is configured to provide odd data loaded on a second input and output data line. The data selection circuit is connected to the first and second sense amplifiers and is configured to provide output data loaded on a single data line, and the data processing circuit connected to the data selection circuit and configured to transfer the even data and the odd data in first and second data paths. The even data and the odd data are combined into the output data of the data selection circuit, and the data selection circuit selects the output data in response to a least significant bit of a column address and transfers the selected data on the single data line in response to a clock signal.Type: ApplicationFiled: March 22, 2010Publication date: September 22, 2011Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.Inventor: CHUNG ZEN CHEN
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Publication number: 20110215850Abstract: A method for tracking a delay locked loop (DLL) clock is described. An external clock signal is allowed to pass through delay cells of a DLL during a first period of the external clock signal when a transition edge of a track signal applied on the DLL occurs. Then, when a transition edge of a sensing signal applied on the DLL occurs at a start of a second period of the external clock signal, the external clock signal is inhibited to pass through the delay cells and the number of the delay cells through which the external signal pass during the first period of the external clock signal is counted. When a reset signal is asserted, a delay time of each delay cell is reset such that a ratio of the delay time to the period of the external clock signal is kept from 10% to 15%.Type: ApplicationFiled: March 3, 2010Publication date: September 8, 2011Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.Inventor: Chung-Zen Chen
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Publication number: 20110188308Abstract: An over erase correction method of a flash memory apparatus is provided. The flash memory apparatus includes at least a microprocessor, a memory array, a bit line exchange unit and a column decoder. By controlling the column decoder of the flash memory during a period of the over-erase correction, the column decoder outputs control signals to the bit line exchange unit for selecting at least one of the bit lines according to a magnitude of the bit line leakage current. The drop in the charge pump voltage due to the bit line leakage current is reduced, and thus, the over-erase correction is executed effectively during the period of the over-erase correction.Type: ApplicationFiled: February 3, 2010Publication date: August 4, 2011Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.Inventor: Chung-Zen Chen
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Publication number: 20110176369Abstract: A suitable erase verification (ERSV) method of a flash memory apparatus is provided, which is different from the conventional ERSV method. That is, by managing the ERSV operation on the flash memory after at least once of erase operation, a flash memory controller in the flash memory apparatus selectively assigns at least one of de-selected sectors instead of all of the de-selected sectors to perform the ERSV. Therefore, by managing the ERSV operation on the flash memory, the time for the ERSV operation thereon is reduced.Type: ApplicationFiled: January 19, 2010Publication date: July 21, 2011Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.Inventor: Chung-Zen Chen
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Publication number: 20110170366Abstract: A method for determining a temperature in a circuit comprises receiving a periodic signal. A frequency of the periodic signal is an increasing function of temperature. A number of oscillations of the periodic signal is determined during a time interval. A length of the time interval is an increasing function of temperature. The temperature is based on the determined number of oscillations.Type: ApplicationFiled: March 22, 2011Publication date: July 14, 2011Applicant: MOSAID TECHNOLOGIES INCORPORATEDInventor: Chung Zen Chen
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Patent number: 7929366Abstract: A temperature detector in an integrated circuit comprises a temperature-dependent voltage generator, a ring oscillator, a timer and a clock-driven recorder. The temperature-dependent voltage generator is configured to generate at least one temperature-dependent voltage. The ring oscillator is configured to generate a clock signal, which is affected by one of the at least one temperature-dependent voltage. The timer is configured to generate a time-out signal, which is affected by one of the temperature-dependent voltage. The clock-driven recorder has a clock input terminal in response to the clock signal and time-out signal.Type: GrantFiled: November 16, 2009Date of Patent: April 19, 2011Assignee: Mosaid Technologies IncorporatedInventor: Chung Zen Chen
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Patent number: 7924610Abstract: A method for conducting an over-erase correction describes the steps of: conducting a first erase and verification operation; using an FN soft program to correct over-erased cells if bit line leakage is found after the first erase and verification operation; conducting a second erase and verification operation; and using a hot carrier HC soft program to correct over-erased cells if bit line leakage is found after the second erase and verification operation.Type: GrantFiled: January 8, 2009Date of Patent: April 12, 2011Assignee: Elite Semiconductor Memory Technology Inc.Inventors: Chung Zen Chen, Chung Shan Kuo, Tzeng Ju Hsue, Ching Tsann Leu
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Patent number: 7847617Abstract: A charge pump comprises a ring oscillator and a pumping circuit. The ring oscillator provides a plurality of oscillating clocks. The pumping circuit includes a plurality of pumping blocks coupled to each other for outputting a boosted voltage, and each pumping block is connected to a corresponding oscillating clock.Type: GrantFiled: December 11, 2007Date of Patent: December 7, 2010Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Chung Zen Chen
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Patent number: 7804326Abstract: A voltage level shifter comprises a voltage adjustment circuit, an inverter, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second NMOS transistor. The voltage adjustment circuit is configured for receiving a first voltage and a second voltage and for generating an adjustment voltage. When the first voltage is higher than the second voltage, the adjustment voltage is substantially equal to the first voltage, and when the first voltage is lower than the second voltage, the adjustment voltage is substantially equal to the second voltage.Type: GrantFiled: November 30, 2009Date of Patent: September 28, 2010Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Chung-Zen Chen
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Publication number: 20100172188Abstract: A method for conducting an over-erase correction comprises the steps of: conducting a first erase and verification operation; using an FN soft program to correct over-erased cells if bit line leakage is found after the first erase and verification operation; conducting a second erase and verification operation; and using a hot carrier HC soft program to correct over-erased cells if bit line leakage is found after the second erase and verification operation.Type: ApplicationFiled: January 8, 2009Publication date: July 8, 2010Applicant: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.Inventors: CHUNG ZEN CHEN, CHUNG SHAN KUO, TZENG JU HSUE, CHING TSANN LEU