Patents by Inventor Chyi-Shyuan Chern

Chyi-Shyuan Chern has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100140716
    Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a first region and a second region; a first gate stack of an n-type field-effect transistor (FET) in the first region; and a second gate stack of a p-type FET in the second region. The first gate stack includes a high k dielectric layer on the semiconductor substrate, a first crystalline metal layer in a first orientation on the high k dielectric layer, and a conductive material layer on the first crystalline metal layer. The second gate stack includes the high k dielectric layer on the semiconductor substrate, a second crystalline metal layer in a second orientation on the high k dielectric layer, and the conductive material layer on the second crystalline metal layer.
    Type: Application
    Filed: December 10, 2008
    Publication date: June 10, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Simon Su-Horng Lin, Chi-Ming Yang, Chyi Shyuan Chern, Chin-Hsiang Lin
  • Patent number: 7732344
    Abstract: A method for fabricating a integrated circuit with improved performance is disclosed. The method comprises providing a substrate; forming a hard mask layer over the substrate; forming protected portions and unprotected portions of the hard mask layer; performing a first etching process, a second etching process, and a third etching process on the unprotected portions of the hard mask layer, wherein the first etching process partially removes the unprotected portions of the hard mask layer, the second etching process treats the unprotected portions of the hard mask layer, and the third etching process removes the remaining unprotected portions of the hard mask layer; and performing a fourth etching process to remove the protected portions of the hard mask layer.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: June 8, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang Wen Tsai, Matt Yeh, Ming-Jun Wang, Shun Wu Lin, Chi-Chun Chen, Zin-Chang Wei, Chyi-Shyuan Chern
  • Publication number: 20100109098
    Abstract: A method of fabricating a gate of a semiconductor device is provided. In an embodiment, the method includes forming a gate dielectric layer on a semiconductor substrate. An interface layer is formed on the gate dielectric layer. In an embodiment, the gate dielectric layer includes HfO2 and the interface layer includes Hf—N. A work function metal layer may be formed on the interface layer. A device is also provided.
    Type: Application
    Filed: December 19, 2008
    Publication date: May 6, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Simon Su-Horng Lin, Chi-Ming Yang, Chyi-Shyuan Chern, Chin-Hsiang Lin
  • Publication number: 20100112912
    Abstract: A retainer ring and a method of using the retainer ring are provided. The retainer ring has openings along a bottom surface. Grooves encompass the openings and extend to an interior portion of the retainer ring wherein a semiconductor wafer may be held. In operation, a semiconductor wafer is placed inside the retainer ring. As the retainer ring and the semiconductor wafer are moved relative to an underlying polishing pad, slurry is dispensed through the openings in the retainer ring. The grooves in the retainer ring allow the slurry to flow from the openings to the interior portion of the retainer ring and the semiconductor wafer.
    Type: Application
    Filed: January 6, 2010
    Publication date: May 6, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Soon Kang Huang, Chih-Lung Lin, Chyi-Shyuan Chern
  • Patent number: 7666068
    Abstract: A retainer ring and a method of using the retainer ring are provided. The retainer ring has openings along a bottom surface. Grooves encompass the openings and extend to an interior portion of the retainer ring wherein a semiconductor wafer may be held. In operation, a semiconductor wafer is placed inside the retainer ring. As the retainer ring and the semiconductor wafer are moved relative to an underlying polishing pad, slurry is dispensed through the openings in the retainer ring. The grooves in the retainer ring allow the slurry to flow from the openings to the interior portion of the retainer ring and the semiconductor wafer.
    Type: Grant
    Filed: May 21, 2007
    Date of Patent: February 23, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Soon Kang Huang, Chih-Lung Lin, Chyi-Shyuan Chern
  • Publication number: 20080293339
    Abstract: A retainer ring and a method of using the retainer ring are provided. The retainer ring has openings along a bottom surface. Grooves encompass the openings and extend to an interior portion of the retainer ring wherein a semiconductor wafer may be held. In operation, a semiconductor wafer is placed inside the retainer ring. As the retainer ring and the semiconductor wafer are moved relative to an underlying polishing pad, slurry is dispensed through the openings in the retainer ring. The grooves in the retainer ring allow the slurry to flow from the openings to the interior portion of the retainer ring and the semiconductor wafer.
    Type: Application
    Filed: May 21, 2007
    Publication date: November 27, 2008
    Inventors: Soon Kang Huang, Chih-Lung Lin, Chyi-Shyuan Chern
  • Publication number: 20070082581
    Abstract: A system of process control is provided. The system comprises a first processing tool, a first sensor, a second processing tool, and a processor. The first processing tool processes a first workpiece. The first sensor provides real-time monitoring (RTM) data of the first processing tool while processing the first workpiece. The second processing tool processes the first workpiece subsequent to the first processing tool. The processor adjusts, according to the real-time monitoring data and a preset program, the first processing tool for processing a second workpiece, and the second processing tool for processing the first workpiece.
    Type: Application
    Filed: October 7, 2005
    Publication date: April 12, 2007
    Inventors: Volume Chien, Chyi-Shyuan Chern, Yu Yuan Kuo, Ming-Te Mo
  • Publication number: 20070068818
    Abstract: An electroplating system is provided. The system comprises a reaction tank, a tube, and a video bubble detector. The reaction tank, having a first diameter, contains a plating solution. The tube, connecting to the reaction tank, comprises an inflow tube and a branch, wherein the inflow tube inputs the plating solution into the reaction tank, and the branch has an enlarged part having the first diameter. The video bubble detector, mounted on the enlarged part of the branch, detects the presence of a bubble in the plating solution flowing through the branch.
    Type: Application
    Filed: September 28, 2005
    Publication date: March 29, 2007
    Inventors: Ming-Da Guo, Pin-Chieh Hu, Hung-Cheng Chen, Kuan-Hsiao Lin, Wen-Chang Peng, Hsiao-Pin Shih, Chyi-Shyuan Chern
  • Patent number: 7195537
    Abstract: A system of process control is provided. The system comprises a first processing tool, a first sensor, a second processing tool, and a processor. The first processing tool processes a first workpiece. The first sensor provides real-time monitoring (RTM) data of the first processing tool while processing the first workpiece. The second processing tool processes the first workpiece subsequent to the first processing tool. The processor adjusts, according to the real-time monitoring data and a preset program, the first processing tool for processing a second workpiece, and the second processing tool for processing the first workpiece.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: March 27, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Volume Chien, Chyi-Shyuan Chern, Yu Yuan Kuo, Ming-Te Mo