Patents by Inventor Chyi-Shyuan Chern

Chyi-Shyuan Chern has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170205705
    Abstract: A method for manufacturing a pellicle includes: providing a supporting substrate; forming an oxide layer over the supporting substrate; forming a metal layer over the oxide layer; forming a graphene layer over the metal layer; and removing at least a portion of the supporting substrate and the oxide layer. An associated method includes: providing a supporting substrate; forming a first silicon carbide (SiC) layer or a diamond layer over the supporting substrate; forming a graphene layer over the SiC layer or the diamond layer; and removing at least a portion of the supporting substrate and the first silicon carbide (SiC) layer or the diamond layer; wherein the pellicle is at least partially transparent to extreme ultraviolet (EUV) radiation. An associated pellicle is also disclosed.
    Type: Application
    Filed: January 15, 2016
    Publication date: July 20, 2017
    Inventors: Jeng-Shin Ma, Tsiao-Chen Wu, Chi-Ming Yang, Chyi Shyuan Chern, Chih-Cheng Lin, Yun-Yue Lin
  • Publication number: 20170022611
    Abstract: An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's.
    Type: Application
    Filed: April 7, 2015
    Publication date: January 26, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Lin CHANG, Hsin-Hsien WU, Zin-Chang WEI, Chi-Ming YANG, Chyi Shyuan CHERN, Jun-Lin YEH, Jih-Jse LIN, Jo Fei WANG, Ming-Yu FAN, Jong-I MOU
  • Patent number: 9379299
    Abstract: An apparatus includes a wafer with a number of openings therein. For each opening, an LED device is coupled to a conductive carrier and the wafer in a manner so that each of the coupled LED device and a portion of the conductive carrier at least partially fill the opening. A method of fabricating an LED device includes forming a number of openings in a wafer. The method also includes coupling light-emitting diode (LED) devices to conductive carriers. The LED devices with conductive carriers at least partially fill each of the openings.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: June 28, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Hsing-Kuo Hsia, Chih-Kuang Yu, Hung-Yi Kuo, Chyi Shyuan Chern
  • Patent number: 9349712
    Abstract: The present disclosure provides one embodiment of a light-emitting structure. The light-emitting structure includes a carrier substrate having first metal features; a transparent substrate having second metal features; a plurality of light-emitting diodes (LEDs) bonded with the carrier substrate and the transparent substrate, sandwiched between the carrier substrate and the transparent substrate; and metal pillars bonded to the carrier substrate and the transparent substrate, each of the metal pillars being disposed between adjacent two of the plurality of LEDs, wherein the first metal features, the second metal features and the metal pillars are configured to electrically connect the plurality of LEDs.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: May 24, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Chih-Kuang Yu, Chyi Shyuan Chern
  • Patent number: 9324624
    Abstract: The present disclosure involves a method of fabricating a light-emitting diode (LED) wafer. The method first determines a target surface morphology for the LED wafer. The target surface morphology yields a maximum light output for LEDs on the LED wafer. The LED wafer is etched to form a roughened wafer surface. Thereafter, using a laser scanning microscope, the method investigates an actual surface morphology of the LED wafer. Afterwards, if the actual surface morphology differs from the target surface morphology beyond an acceptable limit, the method repeats the etching step one or more times. The etching is repeated by adjusting one or more etching parameters.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: April 26, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Chyi-Shyuan Chern, Hsin-Hsien Wu, Yung-Hsin Yang, Ching-Hua Chiu
  • Patent number: 9324910
    Abstract: A device includes: a substrate; and a doped III-V compound layer disposed over the substrate; wherein: the doped III-V compound layer includes an upper boundary; the upper boundary has a micro-roughened texture and a macro-roughened texture where the micro-roughened texture located on; and the upper boundary includes dopant ions that are not present in a remainder of the doped III-V compound layer underneath the upper boundary.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: April 26, 2016
    Assignee: Epistar Corporation
    Inventors: Hsin-Hsien Wu, Chyi Shyuan Chern, Chun-Lin Chang, Ching-Wen Hsiao, Kuang-Huan Hsu
  • Patent number: 9287478
    Abstract: A plurality of conductive pads are disposed on a substrate. A plurality of semiconductor dies are each disposed on a respective one of the conductive pads. A mold device is positioned over the substrate. The mold device contains a plurality of recesses that are each configured to accommodate a respective one of the semiconductor dies underneath.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: March 15, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Chyi Shyuan Chern, Hsin-Hsien Wu, Chih-Kuang Yu, Hung-Yi Kuo
  • Patent number: 9224636
    Abstract: A method includes forming an opening in a substrate, and the opening completely extends through the substrate. A recast material is formed on sidewalls of the substrate exposed by the opening. A first chemical is applied in the opening to remove the recast material, wherein a residue of the first chemical remains on portions of the sidewalls after the applying of the first chemical. Moreover, A second chemical is applied in the opening to remove the residue of the first chemical, and the second chemical is different from the first chemical.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: December 29, 2015
    Assignee: TSMC SOLID STATE LIGHTING LTD.
    Inventors: Chyi Shyuan Chern, Hsin-Hsien Wu, Chun-Lin Chang, Hsing-Kuo Hsia, Hung-Yi Kuo
  • Patent number: 9214543
    Abstract: A gate structure including a substrate and a gate dielectric layer formed over the substrate. The gate structure further includes a workfunction layer over the gate dielectric layer and spacers enclosing the gate dielectric layer and the workfunction layer. A top surface of a portion of the workfunction layer in contact with sidewalls of the spacer is a same distance from the gate dielectric layer as a top surface of a center portion of the work function layer.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: December 15, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Simon Su-Horng Lin, Chi-Ming Yang, Chyi Shyuan Chern, Chin-Hsiang Lin
  • Patent number: 9099632
    Abstract: A package structure includes: a substrate having a first side and a second side opposite to the first side; a metal layer disposed over at least a portion of the second side of the substrate; a light-reflective layer disposed over the first side of the substrate; and a photonic device bonded to the light-reflective layer from the first side. A segment of the metal layer extends through the substrate from the first side to the second side, and a portion of the substrate is completely enclosed in a cross-sectional view by the metal layer. The package structure is free of a bonding wire over the second side of the substrate.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: August 4, 2015
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Chyi Shyuan Chern, Wen-Chien Fu, Hsing-Kuo Hsia, Chih-Kuang Yu, Ching-Hua Chiu, Hung-Yi Kuo
  • Publication number: 20150211122
    Abstract: An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's.
    Type: Application
    Filed: April 7, 2015
    Publication date: July 30, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Lin CHANG, Hsin-Hsien WU, Zin-Chang WEI, Chi-Ming YANG, Chyi Shyuan CHERN, Jun-Lin YEH, Jih-Jse LIN, Jo Fei WANG, Ming-Yu FAN, Jong-I MOU
  • Publication number: 20150162315
    Abstract: The present disclosure provides one embodiment of a light-emitting structure. The light-emitting structure includes a carrier substrate having first metal features; a transparent substrate having second metal features; a plurality of light-emitting diodes (LEDs) bonded with the carrier substrate and the transparent substrate, sandwiched between the carrier substrate and the transparent substrate; and metal pillars bonded to the carrier substrate and the transparent substrate, each of the metal pillars being disposed between adjacent two of the plurality of LEDs, wherein the first metal features, the second metal features and the metal pillars are configured to electrically connect the plurality of LEDs.
    Type: Application
    Filed: February 20, 2015
    Publication date: June 11, 2015
    Inventors: Chih-Kuang Yu, Chyi Shyuan Chern
  • Patent number: 9048186
    Abstract: A method for forming an integrated circuit is provided. The method includes forming a gate dielectric structure over a substrate. A titanium-containing sacrificial layer is formed, contacting the gate dielectric structure. The whole titanium-containing sacrificial layer is substantially removed.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: June 2, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo Bin Huang, Hsin-Chien Lu, Ryan Chia-Jen Chen, Chi-Ming Yang, Chyi Shyuan Chern, Chin-Hsiang Lin
  • Publication number: 20150140703
    Abstract: An apparatus includes a wafer with a number of openings therein. For each opening, an LED device is coupled to a conductive carrier and the wafer in a manner so that each of the coupled LED device and a portion of the conductive carrier at least partially fill the opening. A method of fabricating an LED device includes forming a number of openings in a wafer. The method also includes coupling light-emitting diode (LED) devices to conductive carriers. The LED devices with conductive carriers at least partially fill each of the openings.
    Type: Application
    Filed: January 23, 2015
    Publication date: May 21, 2015
    Inventors: Hsing-Kuo Hsia, Chih-Kuang Yu, Gordon Kuo, Chyi Shyuan Chern
  • Patent number: 9024341
    Abstract: Two or more molded ellipsoid lenses are formed on a packaged LED die by injecting a glue material into a mold over the LED die and curing the glue material. After curing, the refractive index of the lens in contact with the LED die is greater than the refractive index of the lens not directly contacting the LED die. At least one phosphor material is incorporated into the glue material for at least one of the lenses not directly contacting the LED die. The lens directly contacting the LED die may also include one or more phosphor material. A high refractive index coating may be applied between the LED die and the lens.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Wen Lee, Shang-Yu Tsai, Tien-Ming Lin, Chyi Shyuan Chern, Hsin-Hsien Wu, Fu-Wen Liu, Huai-En Lai, Yu-Sheng Tang
  • Patent number: 9023664
    Abstract: An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Lin Chang, Hsin-Hsien Wu, Zin-Chang Wei, Chi-Ming Yang, Chyi-Shyuan Chern, Jun-Lin Yeh, Jih-Jse Lin, Jo-Fei Wang, Ming-Yu Fan, Jong-I Mou
  • Patent number: 9000455
    Abstract: A shadow mask assembly includes a securing assembly configured to hold a substrate that is configured to hold a plurality of dies. The securing assembly includes a number of guide pins and a shadow mask comprising holes for the guide pins, said holes allowing the guide pins freedom of motion in one direction. The securing assembly includes a number of embedded magnets configured to secure the shadow mask to the securing assembly.
    Type: Grant
    Filed: March 10, 2013
    Date of Patent: April 7, 2015
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Ming-Shing Lee, Chyi-Shyuan Chern, Hsin-Hsien Wu, Yung-Chang Chen, Ming-Hua Lo, Chu-Ching Tsai
  • Patent number: 8993447
    Abstract: An apparatus includes a wafer with a number of openings therein. For each opening, an LED device is coupled to a conductive carrier and the wafer in a manner so that each of the coupled LED device and a portion of the conductive carrier at least partially fill the opening. A method of fabricating an LED device includes forming a number of openings in a wafer. The method also includes coupling light-emitting diode (LED) devices to conductive carriers. The LED devices with conductive carriers at least partially fill each of the openings.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: March 31, 2015
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Hsing-Kuo Hsia, Chih-Kuang Yu, Hung-Yi Kuo, Chyi Shyuan Chern
  • Publication number: 20150083998
    Abstract: A light-emitting diode (LED) element includes a substrate and a GaN layer formed on the substrate. The GaN layer includes a boundary layer including a surface of the GaN opposing the substrate. The surface has a micro-roughening texture and a macro-roughening texture. The boundary layer includes at least one of As, Si, P, Ge, C, B, F, N, Sb, and Xe ions.
    Type: Application
    Filed: December 3, 2014
    Publication date: March 26, 2015
    Inventors: Hsin-Hsien Wu, Chyi Shyuan Chern, Chun-Lin Chang, Ching-Wen Hsiao, Kuang-Huan Hsu
  • Patent number: 8962358
    Abstract: The present disclosure provides one embodiment of a light-emitting structure. The light-emitting structure includes a carrier substrate having first metal features; a transparent substrate having second metal features; a plurality of light-emitting diodes (LEDs) bonded with the carrier substrate and the transparent substrate, sandwiched between the carrier substrate and the transparent substrate; and metal pillars bonded to the carrier substrate and the transparent substrate, each of the metal pillars being disposed between adjacent two of the plurality of LEDs, wherein the first metal features, the second metal features and the metal pillars are configured to electrically connect the plurality of LEDs.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: February 24, 2015
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Chih-Kuang Yu, Chyi Shyuan Chern