Patents by Inventor Chyi-Shyuan Chern
Chyi-Shyuan Chern has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8932921Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a first region and a second region; a first gate stack of an n-type field-effect transistor (FET) in the first region; and a second gate stack of a p-type FET in the second region. The first gate stack includes a high k dielectric layer on the semiconductor substrate, a first crystalline metal layer in a first orientation on the high k dielectric layer, and a conductive material layer on the first crystalline metal layer. The second gate stack includes the high k dielectric layer on the semiconductor substrate, a second crystalline metal layer in a second orientation on the high k dielectric layer, and the conductive material layer on the second crystalline metal layer.Type: GrantFiled: February 6, 2014Date of Patent: January 13, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Horng Lin, Chi-Ming Yang, Chyi Shyuan Chern, Chin-Hsiang Lin
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Patent number: 8906712Abstract: A method includes providing an LED element including a substrate and a gallium nitride (GaN) layer disposed on the substrate. The GaN layer is treated. The treatment includes performing an ion implantation process on the GaN layer. The ion implantation process may provide a roughened surface region of the GaN layer. In an embodiment, the ion implantation process is performed at a temperature of less than approximately 25 degrees Celsius. In a further embodiment, the substrate is at a temperature less than approximately zero degrees Celsius during the ion implantation process.Type: GrantFiled: May 20, 2011Date of Patent: December 9, 2014Assignee: TSMC Solid State Lighting Ltd.Inventors: Hsin-Hsien Wu, Chyi Shyuan Chern, Chun-Lin Chang, Ching-Wen Hsiao, Kuang-Huan Hsu
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Publication number: 20140252380Abstract: A shadow mask assembly includes a securing assembly configured to hold a substrate that is configured to hold a plurality of dies. The securing assembly includes a number of guide pins and a shadow mask comprising holes for the guide pins, said holes allowing the guide pins freedom of motion in one direction. The securing assembly includes a number of embedded magnets configured to secure the shadow mask to the securing assembly.Type: ApplicationFiled: March 10, 2013Publication date: September 11, 2014Applicant: TSMC Solid State Lighting Ltd.Inventors: Ming-Shing Lee, Chyi-Shyuan Chern, Hsin-Hsien Wu, Yung-Chang Chen, Ming-Hua Lo, Chu-Ching Tsai
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Publication number: 20140239323Abstract: A plurality of conductive pads are disposed on a substrate. A plurality of semiconductor dies are each disposed on a respective one of the conductive pads. A mold device is positioned over the substrate. The mold device contains a plurality of recesses that are each configured to accommodate a respective one of the semiconductor dies underneath.Type: ApplicationFiled: May 8, 2014Publication date: August 28, 2014Inventors: Chyi Shyuan Chern, Hsin-Hsien wu, Chih-Kuang Yu, Hung-Yi Kuo
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Publication number: 20140235053Abstract: A method of forming a through-silicon-via (TSV) opening includes forming a TSV opening through a substrate. A recast of a material of the substrate on sidewalls of the TSV opening is removed with a first chemical. The sidewalls of the TSV opening are cleaned with a second chemical by substantially removing a residue of the first chemical.Type: ApplicationFiled: May 1, 2014Publication date: August 21, 2014Inventors: Chyi Shyuan Chern, Hsin-Hsien Wu, Chun-Lin Chang, Hsing-Kuo Hsia, Hung-Yi Kuo
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Publication number: 20140154848Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a first region and a second region; a first gate stack of an n-type field-effect transistor (FET) in the first region; and a second gate stack of a p-type FET in the second region. The first gate stack includes a high k dielectric layer on the semiconductor substrate, a first crystalline metal layer in a first orientation on the high k dielectric layer, and a conductive material layer on the first crystalline metal layer. The second gate stack includes the high k dielectric layer on the semiconductor substrate, a second crystalline metal layer in a second orientation on the high k dielectric layer, and the conductive material layer on the second crystalline metal layer.Type: ApplicationFiled: February 6, 2014Publication date: June 5, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Horng Lin, Chi-Ming Yang, Chyi Shyuan Chern, Chin-Hsiang Lin
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Patent number: 8722436Abstract: A method of light-emitting diode (LED) packaging includes coupling a number of LED dies to corresponding bonding pads on a sub-mount. A mold apparatus having concave recesses housing LED dies is placed over the sub-mount. The sub-mount, the LED dies, and the mold apparatus are heated in a thermal reflow process to bond the LED dies to the bonding pads. Each recess substantially restricts shifting of the LED die with respect to the bonding pad during the heating.Type: GrantFiled: November 25, 2013Date of Patent: May 13, 2014Assignee: TSMC Solid State Lighting Ltd.Inventors: Chyi Shyuan Chern, Hsin-Hsien Wu, Chih-Kuang Yu, Hung-Yi Kuo
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Patent number: 8716128Abstract: A method of forming a through-silicon-via (TSV) opening includes forming a TSV opening through a substrate. A recast of a material of the substrate on sidewalls of the TSV opening is removed with a first chemical. The sidewalls of the TSV opening are cleaned with a second chemical by substantially removing a residue of the first chemical.Type: GrantFiled: April 14, 2011Date of Patent: May 6, 2014Assignee: TSMC Solid State Lighting Ltd.Inventors: Chyi Shyuan Chern, Hsin-Hsien Wu, Chun-Lin Chang, Hsing-Kuo Hsia, Hung-Yi Kuo
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Patent number: 8674451Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a first region and a second region; a first gate stack of an n-type field-effect transistor (FET) in the first region; and a second gate stack of a p-type FET in the second region. The first gate stack includes a high k dielectric layer on the semiconductor substrate, a first crystalline metal layer in a first orientation on the high k dielectric layer, and a conductive material layer on the first crystalline metal layer. The second gate stack includes the high k dielectric layer on the semiconductor substrate, a second crystalline metal layer in a second orientation on the high k dielectric layer, and the conductive material layer on the second crystalline metal layer.Type: GrantFiled: December 10, 2008Date of Patent: March 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Simon Su-Horng Lin, Chi-Ming Yang, Chyi-Shyuan Chern, Chin-Hsiang Lin
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Publication number: 20140065741Abstract: A method of light-emitting diode (LED) packaging includes coupling a number of LED dies to corresponding bonding pads on a sub-mount. A mold apparatus having concave recesses housing LED dies is placed over the sub-mount. The sub-mount, the LED dies, and the mold apparatus are heated in a thermal reflow process to bond the LED dies to the bonding pads. Each recess substantially restricts shifting of the LED die with respect to the bonding pad during the heating.Type: ApplicationFiled: November 25, 2013Publication date: March 6, 2014Applicant: TSMC Solid State Lighting Ltd.Inventors: Chyi Shyuan Chern, Hsin-Hsien Wu, Chih-Kuang Yu, Hung-Yi Kuo
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Patent number: 8623141Abstract: A vacuum system for semiconductor fabrication. The system includes a vacuum chamber for performing a semiconductor fabrication process, a vacuum source, and a piping system fluidly connecting the vacuum chamber to the vacuum source. In one embodiment, the piping system is configured without a horizontal flow path section of piping. In some embodiments, the piping system includes a first piping branch and a second piping branch. The first and second piping branches preferably have a symmetrical configuration with respect to the vacuum source. In yet other embodiments, the first and second piping branches preferably each include a throttle valve.Type: GrantFiled: May 18, 2009Date of Patent: January 7, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Pin Chang, Chyi Shyuan Chern
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Patent number: 8609446Abstract: A method of light-emitting diode (LED) packaging includes coupling a number of LED dies to corresponding bonding pads on a sub-mount. A mold apparatus having concave recesses housing LED dies is placed over the sub-mount. The sub-mount, the LED dies, and the mold apparatus are heated in a thermal reflow process to bond the LED dies to the bonding pads. Each recess substantially restricts shifting of the LED die with respect to the bonding pad during the heating.Type: GrantFiled: October 6, 2011Date of Patent: December 17, 2013Assignee: TSMC Solid State Lighting Ltd.Inventors: Chyi Shyuan Chern, Hsin-Hsien Wu, Chih-Kuang Yu, Hung-Yi Kuo
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Patent number: 8598617Abstract: An LED array comprises a growth substrate and at least two separated LED dies grown over the growth substrate. Each of LED dies sequentially comprise a first conductive type doped layer, a multiple quantum well layer and a second conductive type doped layer. The LED array is bonded to a carrier substrate. Each of separated LED dies on the LED array is simultaneously bonded to the carrier substrate. The second conductive type doped layer of each of separated LED dies is proximate to the carrier substrate. The first conductive type doped layer of each of LED dies is exposed. A patterned isolation layer is formed over each of LED dies and the carrier substrate. Conductive interconnects are formed over the patterned isolation layer to electrically connect the at least separated LED dies and each of LED dies to the carrier substrate.Type: GrantFiled: July 25, 2012Date of Patent: December 3, 2013Assignee: TSMC Solid State Lighting Ltd.Inventors: Chih-Kuang Yu, Chyi Shyuan Chern, Hsing-Kuo Hsia, Hung-Yi Kuo
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Patent number: 8580653Abstract: A method of fabricating an isolation structure including forming a trench in a top surface of a substrate and partially filling the trench with a first oxide, wherein the first oxide is a pure oxide. Partially filling the trench includes forming a liner layer in the trench and forming the first oxide over the liner layer using silane and oxygen precursors at a pressure less than 10 milliTorr (mTorr) and a temperature ranging from about 500° C. to about 1000° C. The method further includes producing a solid reaction product in a top portion of the first oxide. The method further includes sublimating the solid reaction product by heating the substrate in a chamber at a temperature from 100° C. to 200° C. and removing the sublimated solid reaction product by flowing a carrier gas over the substrate. The method further includes filling the trench with a second oxide.Type: GrantFiled: February 25, 2013Date of Patent: November 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tze-Liang Lee, Pei-Ren Jeng, Chu-Yun Fu, Chyi Shyuan Chern, Jui-Hei Huang, Chih-Tang Peng, Hao-Ming Lien
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Publication number: 20130270617Abstract: A gate structure including a substrate and a gate dielectric layer formed over the substrate. The gate structure further includes a workfunction layer over the gate dielectric layer and spacers enclosing the gate dielectric layer and the workfunction layer. A top surface of a portion of the workfunction layer in contact with sidewalls of the spacer is a same distance from the gate dielectric layer as a top surface of a center portion of the work function layer.Type: ApplicationFiled: June 11, 2013Publication date: October 17, 2013Inventors: Simon Su-Horng LIN, Chi-Ming YANG, Chyi Shyuan CHERN, Chin-Hsiang LIN
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Publication number: 20130260484Abstract: The present disclosure involves a method of fabricating a light-emitting diode (LED) wafer. The method first determines a target surface morphology for the LED wafer. The target surface morphology yields a maximum light output for LEDs on the LED wafer. The LED wafer is etched to form a roughened wafer surface. Thereafter, using a laser scanning microscope, the method investigates an actual surface morphology of the LED wafer. Afterwards, if the actual surface morphology differs from the target surface morphology beyond an acceptable limit, the method repeats the etching step one or more times. The etching is repeated by adjusting one or more etching parameters.Type: ApplicationFiled: March 27, 2012Publication date: October 3, 2013Applicant: TSMC Solid State Lighting, Ltd.Inventors: Chyi-Shyuan Chern, Hsin-Hsien Wu, Yung-Hsin Yang, Ching-Hua Chiu
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Publication number: 20130171803Abstract: A method of fabricating an isolation structure including forming a trench in a top surface of a substrate and partially filling the trench with a first oxide, wherein the first oxide is a pure oxide. Partially filling the trench includes forming a liner layer in the trench and forming the first oxide over the liner layer using silane and oxygen precursors at a pressure less than 10 milliTorr (mTorr) and a temperature ranging from about 500° C. to about 1000° C. The method further includes producing a solid reaction product in a top portion of the first oxide. The method further includes sublimating the solid reaction product by heating the substrate in a chamber at a temperature from 100° C. to 200° C. and removing the sublimated solid reaction product by flowing a carrier gas over the substrate. The method further includes filling the trench with a second oxide.Type: ApplicationFiled: February 25, 2013Publication date: July 4, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tze-Liang LEE, Pei-Ren JENG, Chu-Yun FU, Chyi Shyuan CHERN, Jui-Hei HUANG, Chih-Tang PENG, Hao-Ming LIEN
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Patent number: 8466063Abstract: A method of depositing a metal film on a substrate with patterned features includes placing a substrate with patterned features into a photo-induced chemical vapor deposition (PI-CVD) process chamber. The method also includes depositing a metal film by PI-CVD to fill the patterned features from bottom up.Type: GrantFiled: November 22, 2011Date of Patent: June 18, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Simon Su-Horng Lin, Chi-Ming Yang, Chyi Shyuan Chern, Chin-Hsiang Lin
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Publication number: 20130089937Abstract: A method of light-emitting diode (LED) packaging includes coupling a number of LED dies to corresponding bonding pads on a sub-mount. A mold apparatus having concave recesses housing LED dies is placed over the sub-mount. The sub-mount, the LED dies, and the mold apparatus are heated in a thermal reflow process to bond the LED dies to the bonding pads. Each recess substantially restricts shifting of the LED die with respect to the bonding pad during the heating.Type: ApplicationFiled: October 6, 2011Publication date: April 11, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chyi Shyuan Chern, Hsin-Hsien Wu, Chih-Kuang Yu, Hung-Yi Kuo
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Patent number: 8415684Abstract: An apparatus includes a wafer with a number of openings therein. For each opening, an LED device is coupled to a conductive carrier and the wafer in a manner so that each of the coupled LED device and a portion of the conductive carrier at least partially fill the opening. A method of fabricating an LED device includes forming a number of openings in a wafer. The method also includes coupling light-emitting diode (LED) devices to conductive carriers. The LED devices with conductive carriers at least partially fill each of the openings.Type: GrantFiled: November 12, 2010Date of Patent: April 9, 2013Assignee: TSMC Solid State Lighting Ltd.Inventors: Hsing-Kuo Hsia, Chih-Kuang Yu, Gordon Kuo, Chyi Shyuan Chern