Abstract: A system for adjusting display data orientation. The system includes graphics circuitry to send and receive control signals over a set of control lines. The exchange of control signals is governed by a communication protocol. The graphics circuitry is configured to request orientation information via the set of control lines upon detecting a modulation of the set of control lines that is undefined by or illegal under the communication protocol. Based on the orientation information received in response to the request, the graphics circuitry adjusts the orientation of display data transmitted by the graphics circuitry.

Abstract: A system for adjusting display data orientation. The system includes graphics circuitry to send and receive control signals over a set of control lines. The exchange of control signals is governed by a communication protocol. The graphics circuitry is configured to request orientation information via the set of control lines upon detecting a modulation of the set of control lines that is undefined by or illegal under the communication protocol. Based on the orientation information received in response to the request, the graphics circuitry adjusts the orientation of display data transmitted by the graphics circuitry.

Abstract: A method and apparatus which includes a graphics accelerator, circuitry responsive to pixel texture coordinates to select texels and generate therefrom a texture value for any pixel the color of which is to be modified by a texture, and a cache for texels for use by the circuitry to generate texture value for any pixel.

Abstract: A method for caching data defining vertices of a polygon to be displayed by an input/output display device including the steps of providing an index by a vertex for which data is to be cached, storing data defining attributes of a polygon at a vertex in a cache under the index provided, issuing a command signifying a polygon to be manipulated by indicating indices of the vertices of the polygon for which data is cached.

Abstract: A process of coordinating access to a shared resource by a plurality of execution units is provided. Channel control units are used to coordinate access to a shared resource. Each channel control unit reads semaphore values of a semaphore storage unit. In response to synchronization commands and semaphore values, the channel control unit manages the flow of execution instructions to the execution units in order to manage access to the shared resource.

Abstract: A direct memory access (DMA) circuit which is physically positioned with an input/output device, the DMA circuit storing a first reference value pointing to a data structure which describes a buffer portion of system memory in which data is stored for transfer to the I/O device, a value determining a position within the buffer portion of system memory beginning at which a next sequence of data is to be placed, and a value determining a position within the buffer portion of system memory from which a next sequences of data is to be copied to the I/O device, the DMA circuit including circuitry for reading data from the buffer portion of system memory beginning at the position from which a next sequences of data is to be copied and for writing the data read to the I/O device.

Abstract: A method and graphics accelerator apparatus for pipelined generation of output values for a sequence of pixels, with generation of output values for each of at least two textured pixels during each pipeline clock interval. The apparatus includes a combiner stage capable of producing output values during each clock interval of the pipeline, wherein the output values are indicative of a blend of a plurality of textures with a single pixel when the combiner stage operates in a first mode, and the output values are indicative of a blend of an individual texture with two pixels when the combiner stage operates in a second mode.

Abstract: A method, apparatus and article of manufacture are provided for minimizing the number of look-ups in a page table entry (PTE) data structure during mapping of virtual addresses to physical addresses when the physical addresses consist of contiguous addresses. First, a primary virtual address in a PTE data structure is accessed for mapping physical memory. Next, it is determined whether a primary physical address corresponding to the accessed primary virtual address is associated with a physical page having at least one contiguous physical page. If it is determined that such contiguous physical page exists, information relating to both the primary virtual address and any virtual and physical contiguous addresses in the PTE data structure is retrieved in a single look-up.

Abstract: A graphics pipeline including a rasterizing stage producing diffuse color values; a plurality of texture stages producing texture values defining a particular texture; a combiner stage for combining four of a plurality of selectable input values including diffuse color values, texture values furnished by a plurality of texture stages, and proportions for combination of the selectable input values; the combiner stage being capable of providing a result equivalent to a sum of products of any two sets of input values, and a product of two input values.

Abstract: A direct memory access (DMA) circuit which is physically positioned with an input/output device, the DMA circuit storing a first reference value pointing to a data structure which describes a buffer portion of system memory in which data is stored for transfer to the I/O device, a value determining a position within the buffer portion of system memory beginning at which a next sequence of data is to be placed, and a value determining a position within the buffer portion of system memory from which a next sequences of data is to be copied to the I/O device, the DMA circuit including circuitry for reading data from the buffer portion of system memory beginning at the position from which a next sequences of data is to be copied and for writing the data read to the I/O device.

Abstract: An arrangement which utilizes the system memory to store the wave tables used in the generation of high quality sound, and a direct memory access controller to rapidly transfer the portions of the wave tables stored in memory using the system bus so that a sound card may manipulate high quality sounds from wave tables stored directly in system memory without overloading the system bus and without the need for substantial additional memory on the sound card.

Abstract: A direct memory access (DMA) circuit which is physically positioned with an input/output device, the DMA circuit storing a first reference value pointing to a data structure which describes a buffer portion of system memory in which data is stored for transfer to the I/O device, a value determining a position within the buffer portion of system memory beginning at which a next sequence of data is to be placed, and a value determining a position within the buffer portion of system memory from which a next sequences of data is to be copied to the I/O device, the DMA circuit including circuitry for reading data from the buffer portion of system memory beginning at the position from which a next sequences of data is to be copied and for writing the data read to the I/O device.

Abstract: A graphics accelerator including an address remapping memory which straddles slow address spaces and fast address spaces.

Abstract: In a computer display system, a method for mapping textures to three dimensional surfaces divided into a one or more polygons including the steps of determining pixels to be utilized in describing a polygon, selecting a texture map having a scale chosen to reproduce accurately a texture value for pixels for a polygon, determining a plurality of texture coordinates of a pixel at a plurality of positions surrounding a center of the pixel, determining texture values at each of the determined positions, and blending the texture values at the points to produce a texture value for the pixel.

Abstract: A method which evaluates each sequence of pixels provided in a polygon to determine whether the pixels vary linearly, selects sequences of adjacent pixels which vary linearly, determines a processing factor for the sequence of pixels, processes only every one of a selected number of pixels of the sequence, and interpolates the data for pixels of the sequence between the processed pixels after the processed pixels have been processed.

Abstract: A method which derives for each triangle to be rendered the values of the texture map coordinates in world space and the screen space two dimensional coordinates across the polygon, utilizes the values to provide two bounding boxes, compares the values of sides of the bounding boxes, and uses these comparisons to select a texture map of a scale which will provide an accurate color representation of a texture value for the pixels of the polygon.

Abstract: A graphics accelerator pipeline including a combiner stage capable of producing output values during each clock interval of the pipeline which map a plurality of textures to a single pixel or an individual texture to two pixels.

Abstract: A computer system with a multiplexed address bus that is shared by both system memory and by slave devices is described. The slave devices are incorporated into an existing system memory configuration by providing a bus controller to execute a two-cycle address sequence on the multiplexed address bus. The address sequence is followed by a transfer of data. A random latency can exist between the time of receiving address information and the time of receiving data corresponding to the address information. This random latency can be exploited by the system CPU for other computational purposes. The bus controller of the system executes multiple, or pipelined, data writes to the bus before an acknowledgement for the first data write is received. In this scheme, the acknowledgement for the first data write is typically sent during the same time period that the subsequent data writes are being received. Consequently, data transfer acknowledgements overlap data writes.

Abstract: A direct memory access (DMA) circuit which is physically positioned with an input/output device, the DMA circuit storing a first reference value pointing to a data structure which describes a buffer portion of system memory in which data is stored for transfer to the I/O device, a value determining a position within the buffer portion of system memory beginning at which a next sequence of data is to be placed, and a value determining a position within the buffer portion of system memory from which a next sequences of data is to be copied to the I/O device, the DMA circuit including circuitry for reading data from the buffer portion of system memory beginning at the position from which a next sequences of data is to be copied and for writing the data read to the I/O device.

Abstract: An input circuit for an input/output device adapted for use in a computer system in which a command includes information indicating an application program which initiated the command, the input circuit including a first-in first-out (FIFO) buffer circuit having a plurality of stages, each stage providing storage for commands from application programs including both data and an address for the data, a direct memory access circuit for transferring data between a buffer established in system memory by an application program and the FIFO buffer circuit, computer implemented software means for establishing a transfer buffer in system memory, circuitry for determining from a command which application program has initiated the command, and circuitry for assuring that commands from only one application program reside in the FIFO buffer circuit at any time.