Abstract: A circuit for accelerating processing of pixel data being provided to a frame buffer comprising circuitry for determining that pixel values vary linearly over a scan line of a polygon to be rendered, linear interpolation circuitry for providing pixel values using a process of linear interpolation between accurately determined pixel values, and a circuit for collecting pixel values to be written to a frame buffer until a significant number of pixel values may be written together.

Abstract: Apparatus and a method by which the flow of DMA-transferable data from an application program to an input/output device using a direct memory access circuit may be halted when the device is unable to respond to DMA-transferable data sent to it. The apparatus includes circuitry for ascertaining whether the input/output device is able to respond to DMA-transferable data transferred to the input/output device, a circuit for storing the DMA-transferable data transferred to the input/output device to which the input/output device is unable to respond, and circuitry for generating a signal to disable immediately the flow of DMA-transferable data to the input/output device and an interrupt to assure that the DMA-transferable data is handled in an expeditious manner.

Abstract: A circuit for providing a perspective correct transformation of attribute values at positions defining a planar polygon in world space to attribute values at pixels describing the polygon in screen space including a first circuit for determining a series of presetup values defined by coordinates of vertices of the polygon which are constant throughout the polygon, a second circuit for computing setup values for each attribute which are constant throughout the polygon from the presetup values, a third circuit for computing from the setup values for each attribute a result for the attribute which is constant at any pixel describing the polygon, a fourth circuit for determining a reciprocal of a result of a depth attribute computed by the third circuit, and a fifth circuit for combining the values of the result computed by the third circuit for each attribute and the reciprocal value for each pixel of the polygon.

Abstract: A direct memory access (DMA) arrangement having a DMA circuit which is positioned with an input/output device, the DMA circuit including a first register for storing a reference value pointing to a first data structure established by an application program which includes details of a transfer buffer in memory in which data is stored for transfer to the I/O device, two additional registers for storing an address and a range at which the data is stored within the transfer buffer in memory, and a fourth register for storing a reference value pointing to a second data structure which includes details describing a notification area of memory at which a notification from the DMA circuit that a transfer of data has been completed may be stored.

Abstract: An arrangement which utilizes the system memory to store the wave tables used in the generation of high quality sound, and a direct memory access controller to rapidly transfer the portions of the wave tables stored in memory using the system bus so that a sound card may manipulate high quality sounds from wave tables stored directly in system memory without overloading the system bus and without the need for substantial additional memory on the sound card.

Abstract: An input circuit for an input/output device adapted for use in a computer system including a first section having a storage circuit holding physical addresses of input/output devices which are translations of selected input/output bus addresses, and a comparator circuit for testing an address in a command from application programs including both data and an address for the data with the recently accessed addresses to obtain a translation from the storage circuit; and a second section including a hash table including translations of physical addresses to be placed in the storage circuit.

Abstract: A computer system including a central processing unit, a system input/output bus, an input/output device, and an input/output control unit accessed at a physical input/output address for translating addresses and data in commands from applications programs to physical input/output device addresses and for changing the context of an input/output device for which an address translation is furnished.

Abstract: A method of controlling the routing of input/output operations including providing a series of commands expressing connections between sources of data, processing elements, and destinations for data to carry out an input/output operation; compiling a data structure for the input/output operation from the series of commands, the data structure including context defining connections between each of the sources of data, processing elements, and destinations for data; and using the data structure to set connecting context to make connection expressed between each of the sources of data, processing elements, and destinations for data whenever the input/output operation is to be accomplished.

Abstract: An input/output control unit which provides a large amount of input/output address space divisible into areas each of which is a multiple of the system memory management unit page size and thus may be allotted to only one of the individual application programs using a computer system by an input/output device driver. The control unit is able to determine from command addresses provided by the application programs both the application program which is involved in the operation and the address area which has been allotted solely to that application program. This use of these addresses in the input/output address space which have been allotted solely to one application program allows the application programs to write directly to the input/output devices while still maintaining the integrity of the system.

Abstract: An arrangement which provides for storing a single lookup/bypass bit with each pixel stored in a frame buffer to indicate whether the color format used to display that pixel on the output display is to use the lookup tables, and for storing an indication apart from the frame buffer which to indicate the decode format for the pixels stored in the frame buffer and retrieved for display by programs providing graphics output in different color formats. The arrangement allows fifteen bit color formats to be stored in standard sized frame buffers without the addition of memory devices.

Abstract: A frame buffer including a memory array, circuitry for accessing the array, a plurality of latches each capable of storing a plurality of pixel values equivalent to a large portion of a row of pixels in the array which may be read simultaneously from the array, and circuitry for writing simultaneously to the memory cells of a row of the array the data stored in the latches whereby a row of pixels may be read and written back to the array bus in a minimum time period.

Abstract: A digital system which uses an arrangement of one or more parallel FIFO buffers in which each FIFO buffer handles data from only one application program at any time. In order to assure that no data written to a FIFO buffer by an application program will overflow the FIFO buffer, each FIFO buffer includes a flow control register which must be read by the processing unit running the application before writing data to an input/output device. The register stores a value which indicates the amount of space available in the FIFO buffer to which data may be written. Reading this register tells the application program how much data may be written without running the risk of overflowing the data storage area which the input/output device has available.

Abstract: An arrangement which utilizes the system memory to store the wave tables used in the generation of high quality sound, and a direct memory access controller to rapidly transfer the portions of the wave tables stored in memory using the system bus so that a sound card may manipulate high quality sounds from wave tables stored directly in system memory without overloading the system bus and without the need for substantial additional memory on the sound card.

Abstract: Hardware input/output control apparatus for use in a computer system which control apparatus is joined to a plurality of input/output devices, and includes circuitry which responds to commands from unprivileged application programs addressed to input/output devices joined to the hardware input/output apparatus for selecting a context to be placed on an addressed input/output device to function with an application program sending the command.

Abstract: A DMA controller which responds without operating system intervention to virtual addresses provided by application programs, and a memory management unit for providing translations between physical addresses of input/output devices and addresses on a system input/output bus for data transferred by the DMA controller.

Abstract: Apparatus for transferring commands over a system transmission path between first and second components in a digital data system including a first-in first-out circuit having a plurality of stages arranged in the system transmission path, circuitry for generating a first signal to indicate that a component to which a command in the FIFO circuit is directed is unable to handle an operation commanded, and a delay circuit responsive to the first signal for causing the generation of an interrupt request signal after a preselected time.

Abstract: An arrangement providing frame buffer memory for an output display by which single buffer and double buffered application programs may be run singly or simultaneously is described. An array of video random access memory sufficient to store data for at least two complete frames is configured in three different ways depending on the applications being run. When only programs designed to run on a single frame buffer are run, the memory is configured as a single frame buffer. When a single program designed to run on double frame buffers is run, the memory is configured as two visible frame buffers. When multiple programs designed to run on double frame buffers are run, the memory is configured into one visible and one invisible frame buffer. Additionally, apparatus for selecting data to be furnished to the display depending on whether the program operates as a single buffered program, a double buffered program, or a plurality of double buffered programs is provided.

Abstract: An input circuit for an input/output device adapted for use in a computer system in which a command includes information indicating an application program which initiated the command, the input circuit including a first-in first-out (FIFO) buffer circuit having a plurality of stages, each stage providing storage for commands from application programs including both data and an address for the data, circuitry for determining from a command an application program which has initiated a command, and circuitry for assuring that commands from only one application program reside in the FIFO buffer at any time.

Abstract: Hardware input/output address translation apparatus adapted for use in a multitasking computer system including hardware responsive to commands from an unprivileged application program addressed to an input/output address for translating the input/output address to a physical address space of an input/output device and transferring the command to the physical address of an input/output device, and additional hardware responsive to commands from an unprivileged application program addressed to an input/output address for selecting from safe translations of input/output addresses to physical address spaces of input/output devices for the hardware for translating the input/output address to a physical address space of an input/output device.

Abstract: An ordered dithering process by using different sets of dithering patterns for different color components of the source pixel color instead of using the same set of patterns. The sets of dithered patterns are designed in a way that variations in intensity due to dithering of some color components are partially or fully compensated by variations in intensity due to dithering of other color components.