Abstract: An apparatus for implementing, in hardware, clipping and intercoordinate comparison logic in a graphic display subsystem. Clipping is necessary when an object to be displayed is defined as being only partially contained within a pre-determined window on a video display. For example, if a rectangular window is defined in the upper left hand corner of a video display, and a line has been defined which extends from the upper left-hand corner to the lower right-hand corner of the display, the portion of the line which is outside the defined window is not displayed, i.e., it is clipped. Additionally, if a line of text is wider than the window, the portion of the line of text which is outside the window must also be clipped.

Abstract: A method of allocating space in a frame buffer memory which is not used for storing pixels to be displayed currently including the steps of selecting a portion of the memory to be allocated for off-screen memory; determining the size of an area to be allocated; comparing the size of the area to be allocated with portions of the memory available to be allocated for off-screen memory using a memory allocation technique in which the least area considered is at least as great in either its horizontal or its vertical dimension as the greater dimension of the area to be allocated, the comparison being conducted in a pattern which consistently checks first a minimum area followed by three other minimum areas in an area having a size which is the next power of two larger in each dimension than the minimum area, then four more minimum areas in an adjacent area having a size which is the next power of two larger in each dimension than the minimum area than the minimum area in the pattern, the area selected for the seco

Abstract: A predictive caching system for use in computer system having at least one portion of memory in which information is stored for retrieval, a general cache used to speed the operation of accessing such memory, and a processor for controlling the access of the memory comprising apparatus for discerning a pattern of access of the memory, apparatus operating in response to the pattern determined by the apparatus for discerning a pattern of access of the memory for determining a next address which will probably accessed in such memory if the pattern discerned continues, and apparatus for storing the information at the next address determined prior to the next access of the memory whereby the information at the next address is available without the need to access the memory.

Abstract: An apparatus for implementing, in hardware, circuitry for adding a raster offset to screen coordinates in a graphics display subsystem for the purpose of displaying the image in a window which may be moved by a user to an arbitrary position on a screen display. Specifically, a pair of raster offsets, one for X coordinates and one for Y coordinates, are stored in X and Y raster offset registers. The X and Y raster offsets correspond to the offset of an active window from the origin of the screen display. These offsets are added to each coordinate which is to be displayed within the active window in a manner which does not result in any additional overhead.

Abstract: A method for allowing direct graphics access to backup storage areas in frame buffer memory used for retained windows and controlled by a graphics accelerator which includes the steps of establishing a shared memory file in system memory for the backup storage area indicating that the retained windows area initially exists in excess frame buffer memory, the shared memory file having storage to indicate the use of the shared area by a process; generating a page fault whenever access to the graphics accelerator is attempted and the state of another process is stored on the graphics accelerator; and calling a device driver in response to the page fault to switch the context stored on the graphics accelerator to that of the process attempting the access.

Abstract: A computer graphics system comprising apparatus for drawing quadrilateral images on an output display when furnished the vertices of the quadrilateral, apparatus for providing width values for each end of a line to be displayed on an output display which width values are indirectly related to the depth of the ends of the line from the viewer, and apparatus for utilizing the width values to determine vertices of a line to be drawn by the apparatus for drawing a quadrilateral image.

Abstract: A method of implementing a move-draw format to control the operation of a graphics accelerator of a computer system which includes the steps of providing a designation in a process for rendering an element defining the total element being drawn, referring to the type designation to determine whether the graphics accelerator is able to implement an algorithm for such type, and selecting the individual coordinates from the format to implement the process while ignoring the move-draw elements if the graphics accelerator is capable of implementing the algorithm.

Abstract: A graphics accelerator interface apparatus for receiving information to be displayed by a computer and the address of such information. Storing the addresses of vertices of a quadrilateral to be displayed by a computer, translating the addresses of vertices of a quadrilateral into signals representing the relations between each of such vertices and the others of the vertices, selectively decomposing a quadrilateral into line segment portions defining trapezoids which bound sets of scan lines, determining the coordinates of the end points of each scan line within such trapezoids, translating the coordinates of the end points into linear values for display, and storing such information for display on a computer output display.

Abstract: An apparatus and method for using a test window to improve the efficiency of clipping and inter-coordinate images which are to be displayed by a graphic display subsystem. A test window is defined which surrounds a window (the clip window) within which it is desired to render graphical images. Objects are then tested to see if their vertices are outside the test window. The utilization of this window allows for a performance optimization to be made between processing of a clipped object by a hardware based graphics subsystem which incorporates the present invention or by graphic software executed by a general purpose CPU which also interfaces to the graphics display. By properly defining the test window size relative to the clip window, objects which fall totally within the test window, will be rendered faster by the graphics subsystem rather than deferring the object to graphics software. Objects with vertices that fall outside the test window would be deferred to graphics software to render.

Abstract: Apparatus and method for using an index register which cycles modulo 4 for loading registers which contain coordinates of four vertices of quadrilateral objects, including degenerate quadrilateral objects, namely a point, a line and a triangle, which are to be displayed by a graphics display subsystem. In this manner, a software command need only define the minimum number of X,Y coordinate pairs to define the object, i.e., one coordinate pair for a point, two coordinate pairs for a line, three coordinate pairs for a triangle and two coordinate pairs for a rectangle (by defining opposite corners). Additionally, by using an index register according to the present invention, objects can be efficiently replicated.

Abstract: Circuitry for performing high speed operations on certain Boolean raster operations in a workstation whose functions include the display of graphics images using multiple planes and having foreground and background colors. The circuitry includes a logic circuit for determining whether a particular Boolean raster operation is one for which the high speed operation is available. A Boolean raster operation is determined to be available for high speed operation if the outcome of the operation can be determined by reading only one operand, namely the source data. If the other operand, namely the destination data, is needed to determine the outcome if the operation, then the operation is performed normally. Otherwise, the operation may be performed by reading the source data only.

Abstract: A circuit for determining the X values of each end of a series of horizontal scan lines connecting a pair of line segments each of which is defined by a pair of vertices, the horizontal scan lines defining an area to be rendered on a computer output device, comprising first and second circuit portions, each of said circuit portions including apparatus to determine the slope of a line segment, apparatus depending on the slope for determining the beginning and ending X values for each line segment for each scan line in the area to be rendered, apparatus for causing the two circuit portions to begin operation at the same scan line, and apparatus for changing the Y value for each circuit portion to the Y value of the next adjacent scan line at the same time.

Abstract: A method of initiating a write operation for a particular command from a first computer module through a system interface to a second computer module having data registers, and a status register which includes the steps of writing data to the data registers in the second computer module, and determining the status of the status register in the second computer module to cause the initiation of the particular command by which the reading the status of the data registers and issuing the particular command as separate steps are eliminated.

Abstract: The system of the present invention provides for the context switching of devices connected through the system's memory management unit and is particularly useful in a multi-tasking computer system in which multiple processes access the same device. In the method and apparatus of the present invention, devices that are connected to the system through the MMU are controlled using the page fault mechanism of the MMU and the page fault handler in each segment. Addresses are allocated in the process address space for each process to provide for the addressing of the devices and device queues connected through the MMU, such that one device or one device queue is mapped into one segment of each process address space that will access the device. The "valid bits" associated with each page in a segment are turned on/off by the process or operating system in order to control the device.

Abstract: In a computer graphics system in which information defining graphic images to be presented on an output display is available on a scan line basis for a pair of line segments subtending a portion of the an image to be presented. The information includes the slope of each line segment and the addresses of each line segment on each scan line. A circuit comprising two comparator subportions, each of the comparator subportions being adapted to process information regarding one edge of the portion of the image to be presented and including apparatus for receiving first signals representing values of both of the line segments to be procesed for one scan line. Comparing the signals to determine their relative X positions on the scan line, controlling the determination of the relative X positions and the slope of each line segment, and storing one of the signals compared.

Abstract: Handshake circuitry for an asynchronous bus interface system transferring data between first and second computer systems including apparatus for providing signals to indicate to the second computer system that the first system desires to read data at a specified adress of the second system, apparatus for comparing the specified address with addresses of the second system to provide outputs indicating the time required to retrieve data from the specified address, and apparatus operative in response to the output indicating the time required to retrieve data from the second computer to indicate to the first computer system the time at which the information will be available for transfer to the first computer system.

Abstract: An apparatus and method for processing graphical information in a manner such that 1) accesses to a frame buffer in which the graphical information is to be stored result in a minimum of page crossings in the frame buffer; and 2) time spent processing graphical information outside a predetermined clip window is minimized. These two goals are sometimes conflicting and the present invention determines how the graphical information should be processed so that frame buffer accesses are always performed with the least overhead. For a given object which is to be displayed within a defined window, by determining the portions of the object which are inside the window and the portions which are outside the window, it frequently is possible to determine whether the object should be drawn from top to bottom, bottom to top, left to right or right to left so as to minimize page crossings and minimize the time spent processing portions of the object outside a predetermined clip window.

Abstract: Write handshake circuitry for an asynchronous bus interface system transferring data between sending and receiving computer systems including apparatus for providing a pre-acknowledge signal during the idle condition of the interface system to indicate to the sending computer system that the receiving system is ready to accept data, apparatus for synchronizing the pre-acknowledge signal to the clock of the sending computer system during the idle condition of the interface system, apparatus for providing a write signal from the sending computer system to indicate to the receiving computer system that the sending computer system is writing to the receiving computer system, and apparatus in the receiving system for receiving and synchronizing data upon the appearance of the write signal.

Abstract: A first number conversion circuit for converting input numbers in the form of an integer, a floating-point number and a FRACT number into Modulo 256 format for use in connection with a graphic accelerator capable of rapidly manipulating numbers in Modulo 256 format. Also, a second number conversion circuit is disclosed for converting numbers in Modulo 256 format into output numbers in the form of an integer, a floating-point number and a FRACT number after manipulation by the graphic accelerator.

Abstract: A method for clip checking three dimensional images for display on a computer display system. The display system includes a computer having a central processing unit(CPU) coupled to a memory and a cathode ray tube (CRT) display. The method of the present invention includes inputting a plurality of points comprising an image to be displayed, wherein each of the points is described by X,Y,Z and W world coordinates. The points are stored in the memory coupled to the CPU. The CPU executes a viewing algorithm which transforms the world coordinates for each point into view reference coordinates. The view reference coordinates have an origin at the viewpoint of the user, with the Z axis pointed outward in the direction of the display screen. Each of the points of the image are described by clipping bits X Right, X Left, Y Top, Y Bottom, Z Back, and Z Front. The view reference coordinate system permits the user to selectively enable/disable clipping quadrants in X,Y,Z and W space.