Abstract: A mulitplexor implementation of circuitry for performing Boolean raster operation in a workstation whose functions include the display of graphics images using multiple planes and having foreground and background colors. The invented circuitry includes a plane raster-op select circuit and Boolean raster-op circuit. The plane raster-op select circuit selects a Boolean raster operation to be performed for each plane of graphics information as a function of foreground and background color control signals. The selected Boolean raster operation for each plane is then input to set of mulitplexors and the selected Boolean raster operation is performed on the control inputs to the multiplexors which combines source and destination data for each plane according to the selected Boolean operation for that plane.

Abstract: The parallel carry generator calculates the carry for a m bit number within log.sub.2 n+1 gate delays where n is smallest binary ordered number greater than or equal to m. Thus in the parallel carry generation adder of the present invention, the sum is calculated in log.sub.2 n+2 gate delays. Thus, a 32 bit carry computation can be performed in as little as 6 gate delays. This is achieved by breaking down the 32 bit word according to binary ordered values and cascading portions of the calculations required wherein the carry generated for the most significant bit of the lower binary ordered group is used to calculate the carrys for the bits in next higher ordered group. By ordering the bits and the logic circuitry in this manner, the amount of gate delays to perform the carry calculation is minimized without excessively increasing the amount of logic.

Abstract: A matrix arithmetic circuit for processing matrix transformation operations includes a random access memory (RAM) for storing a plurality of numbers in Modulo 256 with multiple tap points numbers format. A multiplier multiplies two of the Modulo 256 numbers in RAM to obtain a product. The product is normalized and added to a third Modulo 256 number stored in the RAM to obtain a result. The result is stored in the RAM and coupled to the data processing system for use in matrix transformation operations.

Abstract: A circuit which computes the scan position of any pixel on the display as the sum of the number of scan lines multiplied by the number of pixels per scan line plus the number of pixels on the scan line to the particular position using an adder for a changing portion of the computation and an incrementer for a constant portion of the computation and combining the two of these to produce a result which accomplishes in a relatively economic fashion what would normally require an inordinate number of gates to obtain a variety of screen resolutions which are not simply powers of two multiples of one another.

Abstract: A method and apparatus for performing anti-aliasing of rendered lines, text and images displayed by a workstation on a video display. The anti-aliasing is performed by logically dividing each addressable frame buffer pixel into sixteen sub-pixels and generating a gray scale value for the displayed pixel that is a function of the number of sub-pixels crossed by a portion of a rendered image. The invented circuitry is part of the circuitry used for combining source and destination data which forms the displayed image namely, an anti-aliasing mask and filter, adder/subtractor logic, saturation logic and anti-aliasing logic.

Abstract: Apparatus and methods for displaying two and three dimensional graphics within a plurality of windows on a display system. The display system includes a central processing unit (CPU) which provides RGB data to a bit-mapped display memory coupled to a cathode ray tube (CRT) display. A Z-buffer memory is provided with a Z-value for each RGB data point corresponding to a point on the object to be displayed. The Z-buffer is organized such that the value of the entire n bit buffer (0 through 2.sup. n-1) identifies the window in which the graphics and/or text is displayed. For windows in which only two dimensional (2D) graphics/text is displayed, the Z-value is the same for both the window and each RGB point of the image. For windows which display three dimensional (3D) graphics, a range of Z-values for the buffer are provided which define the window boundaries. Images to be displayed within a 3D window must have Z-values which fall within the particular window's Z-value range.