Abstract: An arrangement which provides hardware at the game port to provide a direct analog-to-digital conversion of input signals provided by the directional input signals of a joystick without involving the central processing unit in the determination. By determining at the game port the input values, the central processing unit need not have its interrupts disabled, and games may easily function with other application programs in a multi-tasking operating system.

Abstract: A computer system including a central processing unit, a system input/output bus, an input/output device, and an input/output control unit joined to the system input/output bus for translating addresses on the system input/output bus to physical input/output device addresses.

Abstract: A system which uses an arrangement of FIFO buffers which include circuitry to assure that no data written to a FIFO buffer by an application program will overflow the FIFO buffer. Each FIFO buffer includes a flow control register which stores a value which indicates the amount of space available in the FIFO to which data may be written. In order to allow for situations in which data is available at a FIFO buffer which cannot be immediately utilized for some reason, an overflow storage area is provided for storing data transferred to the FIFO buffer in excess of the number of stages of the FIFO circuit which are available to store data. The flow control circuitry also includes circuitry for assuring that data which is placed in the overflow storage area is handled in the appropriate sequence.

Abstract: Apparatus and a method by which an application program writing a series of commands to a single destination on an input/output bus increments the addresses to which the commands are addressed as the commands are written so that the commands may be transferred utilizing the burst mode of the input/output bus, and the device receiving the data decodes a large number of sequential addresses to the same destination so that the input/output device transfers all of the commands in the sequence of addresses to the single destination.

Abstract: Hardware input/output address translation apparatus adapted for use in a multitasking computer system including hardware responsive to commands from an unprivileged application program addressed to an input/output address for translating the input/output address to a physical address space of an input/output device and transferring the command to the physical address of an input/output device, hardware responsive to commands from an unprivileged application program addressed to an input/output address for selecting from safe translations of input/output addresses to physical address spaces of input/output devices for the first hardware means, and apparatus for handling a failure to provide an address translation.

Abstract: Apparatus for emulating input/output devices on an ISA bus using input/output devices on a local bus which includes circuitry for snooping on the bus to capture commands sent to input/output devices the functions of which are to be emulated, circuitry for storing those commands, circuitry for generating new commands in response to the commands which are stored, and circuitry for generating output signals in response to the new commands which output signals replace the output signals produced by the input/output devices on an ISA bus.

Abstract: Hardware input/output control apparatus for use in a computer system which control apparatus is joined to a plurality of input/output devices, and includes circuitry which responds to commands from unprivileged application programs addressed to input/output devices joined to the hardware input/output apparatus for selecting a context to be placed on an addressed input/output device to function with an application program sending the command. Context switching is effected in response to commands from unprivileged application programs without involving the operating system or trusted code.

Abstract: A frame buffer designed to allow frame buffer operations which do not involve new row addresses to be accomplished without the need for a RAS cycle. The elimination of RAS cycles for address loading and similar functions substantially accelerates the operation of the frame buffer both as to functions which do not involve memory array addresses and those which do involve memory array addresses.

Abstract: A hardware encoding circuit which generates a code value unique to a particular computer, stores a password unique to an application program and to the particular computer, tests the stored password against a verification value generated by the hardware encoding program each time the application program is run, and generates an error signal if the stored password and the verification value do not match.

Abstract: Hardware input/output address translation apparatus adapted for use in a multitasking computer system including a circuit which responds to commands from an unprivileged application program addressed to an input/output address for translating the input/output address to a physical address of an input/output device and transferring the command to the physical address of an input/output device, a translation table which responds to commands from an unprivileged application program addressed to an input/output address for selecting from safe translations of input/output addresses to physical address spaces of input/output devices for the first hardware means, each selection of a safe translation being accomplished using an arbitrary name originally provided by the unprivileged application program; and a database of data structures which individually include a physical address of an input/output device and can be copied and named by application programs to provide safe translation for storage in the translation t

Abstract: A flow control circuit for a computer system including a first-in first-out buffer including a register for storing a value indicating the number of stages of the FIFO which are available to store data, circuitry for detecting whether an input/output device is able to process data more rapidly than the FIFO is emptied, and circuitry for providing an value greater than the number of stages actually available for storage in the FIFO if the input/output device is able to process data more rapidly than the FIFO is emptied.

Abstract: Hardware input/output address translation apparatus adapted for use in a multitasking computer system including hardware responsive to commands from an unprivileged application program addressed to an input/output address for translating the input/output address to a physical address space of an input/output device and transferring the command to the physical address of an input/output device, and additional hardware responsive to commands from an unprivileged application program addressed to an input/output address for selecting from safe translations of input/output addresses to physical address spaces of input/output devices for the hardware for translating the input/output address to a physical address space of an input/output device.

Abstract: Apparatus and a method by which the flow of commands to an input/output device may be halted when the device is unable to respond to a command decoded to its address space. The apparatus includes circuitry for ascertaining whether the input/output device is able to respond to a command decoded by the decoding circuit, a circuit for storing the data and address of a command transferred to the input/output device to which the input/output device is unable to respond, and circuitry for generating a signal to disable immediately the flow of commands to the input/output device and an interrupt to assure that the unimplemented command is handled in an expeditious manner.

Abstract: An arrangement for assuring the compatibility of versions of software produced for a particular computer hardware architecture including a hardware version register, apparatus for providing an indication of a version of hardware being utilized to operate a particular version of software, a software version register, apparatus for providing an indication of a version of software being run on the particular version of hardware, apparatus for comparing the version of hardware and the version software, and apparatus responsive to the results of the comparison for setting defaults and enabling circuitry in the hardware so that the version of software runs correctly on the version of hardware.

Abstract: A double buffered output display system including a first frame buffer, a second frame buffer, a multiplexor for furnishing data to an output display from one of the first or the second frame buffers, apparatus for storing a signal indicating that the multiplexor is to select a different frame buffer to furnishing data to an output display, and apparatus for furnishing the stored signal to the multiplexor only at the completion of a frame on a display and before a new frame commences.

Abstract: A frame buffer including an array of memory cells for storing data indicating pixels to be displayed on the output display, row addressing decoding apparatus and column address decoding apparatus for selecting memory cells positioned in the array, apparatus for transferring a row address to the row addressing decoding apparatus upon the assertion of a row address strobe signal, apparatus for transferring a column address to the column address decoding apparatus for decoding upon the assertion of a first column address strobe signal, apparatus for latching a column address and any data necessary to complete the access during the first column address strobe signal, apparatus for accessing the particular column the address of which has been latched during the latching of a next subsequent address of a column to be accessed along with any data necessary to complete the next access during the next subsequent column address strobe signal following the first column address strobe signal.

Abstract: A frame buffer having a memory array, circuitry for accessing the array, a plurality of color value registers for storing a plurality of color values which may be written to the array, and circuitry for writing to the memory cells a data representing a single pixel, for writing simultaneously to the memory cells data representing a number of pixels equal to the number of conductors on the data bus, or for writing simultaneously to the memory cells data representing an entire row of pixels of the array.

Abstract: A frame buffer designed to be coupled to a data bus and to an output display in a computer system, the frame buffer including an array of memory cells for storing data indicating pixels to be displayed on the output display, address decoding apparatus for controlling access to the array, the address decoding apparatus including column address decoding apparatus for selecting groups of adjacent columns of the array, a plurality of apparatus for selectively writing to each of the columns of any of said groups of adjacent columns, a plurality of color value registers, latching apparatus for storing pixel data equivalent to a row of pixel data to be displayed on the output display, apparatus for writing pixel data from selected groups of adjacent columns of the array to the latching apparatus, and apparatus for connecting either selected ones of the color value registers, the latches, or the data bus to the apparatus for selectively writing to each of the columns of any of said groups of adjacent columns.

Abstract: A frame buffer for accelerating the display of graphics data on an output display device which frame buffer includes a pair of color value registers each of which may be loaded with color values prior to writing to the frame buffer. Selection means are provided for selecting pixel data from the bus, from a first of the color value registers, from the second of the color value registers, or from both color value registers simultaneously. When data is written to the frame buffer from color value registers it may be written to a number of pixel positions simultaneously.

Abstract: In a computer system having a frame buffer, apparatus for providing an overlay for the frame buffer, and a digital-to-analog converter for furnishing analog signals from the frame buffer to a pedestal setup display monitor, the digital-to-analog converter including apparatus for furnishing a blank level substantially below the lowest level of the analog signal desired to be visible on the monitor during retrace periods when used with a pedestal setup display monitor, the improvement including apparatus for allowing the system to utilize zero setup display monitors including apparatus for disabling the apparatus for furnishing a blank level when the computer system is used with a zero setup display monitor, and apparatus for causing the apparatus for providing an overlay for the frame buffer to furnish signals indicating a black level during retrace periods when the computer system is used with a zero setup display monitor.