Patents by Inventor Dae-Seok Byeon

Dae-Seok Byeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Nonvolatile memory device and nonvolatile memory system employing same
    Patent number: 8432741
    Abstract: A nonvolatile memory device comprises a memory cell array, a row selection circuit and a voltage generator. The memory cell array comprises a first dummy memory cell, a second dummy memory cell, and a NAND string comprising a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor through the first dummy memory cell and the second dummy memory cell. During a read-out operation mode, a dummy read-out voltage is applied to a first dummy wordline coupled to the first dummy memory cell, and to a second dummy wordline coupled to the second dummy memory cell. The dummy read-out voltage has a lower magnitude than a read-out voltage applied to an unselected memory cell during the read-out operation mode.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: April 30, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Jae Lee, Dae-Seok Byeon, Hyun-Chul Ha
  • Multi-bit flash memory device and method of analyzing flag cells of the same
    Patent number: 8218371
    Abstract: Disclosed is a multi-bit flash memory device which includes a memory cell array and a control circuit. The memory cell array has multiple memory cells and multiple flag cells. The control circuit determines whether the flag cells are programmed, based on a reference corresponding to a read margin of the flag cells, and controls a program operation of the memory cells in response to the determination.
    Type: Grant
    Filed: May 18, 2009
    Date of Patent: July 10, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dae-Seok Byeon
  • NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY SYSTEM EMPLOYING SAME
    Publication number: 20120170370
    Abstract: A nonvolatile memory device comprises a memory cell array, a row selection circuit and a voltage generator. The memory cell array comprises a first dummy memory cell, a second dummy memory cell, and a NAND string comprising a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor through the first dummy memory cell and the second dummy memory cell. During a read-out operation mode, a dummy read-out voltage is applied to a first dummy wordline coupled to the first dummy memory cell, and to a second dummy wordline coupled to the second dummy memory cell. The dummy read-out voltage has a lower magnitude than a read-out voltage applied to an unselected memory cell during the read-out operation mode.
    Type: Application
    Filed: March 14, 2012
    Publication date: July 5, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung-Jae LEE, Dae-Seok BYEON, Hyun-Chul HA
  • NON-VOLATILE MEMORY DEVICE AND A METHOD FOR OPERATING THE DEVICE
    Publication number: 20120147669
    Abstract: A method for operating a non-volatile memory device includes programming a memory cell and not programming a flag cell during first to nth (n is a natural number equal to or greater than 1) program loops, and programming the memory cell and the flag cell during (n+1)th to mth (m is a natural number greater than n) program loops.
    Type: Application
    Filed: November 23, 2011
    Publication date: June 14, 2012
    Inventor: Dae-Seok Byeon
  • Nonvolatile memory device and nonvolatile memory system employing same
    Patent number: 8154927
    Abstract: A nonvolatile memory device comprises a memory cell array, a row selection circuit and a voltage generator. The memory cell array comprises a first dummy memory cell, a second dummy memory cell, and a NAND string comprising a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor through the first dummy memory cell and the second dummy memory cell. During a read-out operation mode, a dummy read-out voltage is applied to a first dummy wordline coupled to the first dummy memory cell, and to a second dummy wordline coupled to the second dummy memory cell. The dummy read-out voltage has a lower magnitude than a read-out voltage applied to an unselected memory cell during the read-out operation mode.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: April 10, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Jae Lee, Dae-Seok Byeon, Hyun-Chul Ha
  • Non-volatile memory device and system having reduced bit line bias time
    Patent number: 8050104
    Abstract: A non-volatile memory device and system are provided. The non-volatile memory device including; a memory cell array of memory blocks, and a bit line bias block connected to the bit lines and configured to precharge the bit lines, a page buffer precharging the plurality of bit lines and sensing data stored in the memory block via the bit lines, and a controller controlling the bit line bias block to simultaneously precharge the bit lines with the page buffer, thereby reducing the bit line bias time.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: November 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dae Seok Byeon
  • Flash memory device and program method of flash memory device using different voltages
    Patent number: 8045380
    Abstract: A flash memory and a program method of the flash memory include applying a pass voltage to word lines to boost a channel voltage, which is discharged to a ground voltage. A program voltage is applied to a selected word line and a local voltage is applied to at least one word line supplied with the pass voltage while the program voltage is being applied to the selected word line. The local voltage is lower than the pass voltage and equal to or higher than the ground voltage. The boosted channel voltage may be discharged before the program voltage is applied to the selected word line.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: October 25, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Seok Byeon, Young-Ho Lim
  • Flash memory device and method of controlling flash memory device
    Patent number: 7974125
    Abstract: A flash memory device includes multiple memory blocks, a decoder configured to select at least one of the memory blocks in response to block select signals, a controller configured to generate the block select signals in response to a block address and to generate a flag signal when the block address corresponds to a bad block, and an output buffer configured to output fixed data in response to the flag signal indicating that the block address corresponds to the bad block. When the block address corresponds to a bad block, the controller generates the block select signals to cause the decoder to interrupt selection of a memory block corresponding to the block address.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: July 5, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Seok Byeon, Young-Ho Lim
  • Flash memory device operating at multiple speeds
    Patent number: 7957201
    Abstract: A method of operating a flash memory device includes a first operating mode and a second operating mode having different operating speeds. Each one of the first and second operating modes includes a bit line set-up interval and at least one additional interval. The flash memory is divided into first and second mats connected to respective first and second R/W circuits. During the bit line set-up interval of the second operating mode, the flash memory controls operation of both the first and second R/W circuits in a time division approach to stagger respective peak current intervals for the first and second mats.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: June 7, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dae-Seok Byeon
  • NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY SYSTEM EMPLOYING SAME
    Publication number: 20110075484
    Abstract: A nonvolatile memory device comprises a memory cell array, a row selection circuit and a voltage generator. The memory cell array comprises a first dummy memory cell, a second dummy memory cell, and a NAND string comprising a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor through the first dummy memory cell and the second dummy memory cell. During a read-out operation mode, a dummy read-out voltage is applied to a first dummy wordline coupled to the first dummy memory cell, and to a second dummy wordline coupled to the second dummy memory cell. The dummy read-out voltage has a lower magnitude than a read-out voltage applied to an unselected memory cell during the read-out operation mode.
    Type: Application
    Filed: August 25, 2010
    Publication date: March 31, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung-Jae LEE, Dae-Seok BYEON, Hyun-Chul HA
  • Non-volatile memory devices and systems including bad blocks address re-mapped and methods of operating the same
    Patent number: 7916540
    Abstract: A method of operating a non-volatile memory device included in a memory card can be provided by re-mapping addresses of bad blocks in a first non-volatile MAT in a memory card and re-mapping addresses of bad blocks in a second non-volatile MAT in the memory card, the second non-volatile MAT including blocks that are address mapped with blocks in the first non-volatile MAT. Also a method of scanning a non-volatile memory device for bad blocks can be provided by sequentially scanning blocks in a non-volatile memory device for data indicating that a respective block is a bad block starting at a starting block address that is above a lowermost block address of the non-volatile memory device, wherein the starting block address is based on a yield for the non-volatile memory device.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: March 29, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dae Seok Byeon
  • Method of programming flash memory device
    Patent number: 7911850
    Abstract: Flash memory devices include a memory array having a plurality of NAND strings of EEPROM cells therein. A word line driver is provided to improve programming efficiency. The word line driver is electrically coupled to the memory array by a plurality of word lines. The word line driver includes a plurality of pass voltage switches. These switches have outputs electrically coupled by diodes to the plurality of word lines. Methods of programming flash memory devices include applying a pass voltage to a plurality of unselected word lines in a non-volatile memory array while simultaneously applying a sequentially ramped program voltage to a selected word line in the non-volatile memory array. The sequentially ramped program voltage has a minimum value that is clamped by a word line driver to a level not less than a value of the pass voltage.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: March 22, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Hyuk Chae, Dae-Seok Byeon
  • Flash memory device operating at multiple speeds
    Patent number: 7898871
    Abstract: A method of operating a flash memory device includes a first operating mode and a second operating mode having different operating speeds. Each one of the first and second operating modes includes a bit line set-up interval and at least one additional interval. The flash memory is divided into first and second mats connected to respective first and second R/W circuits. During the bit line set-up interval of the second operating mode, the flash memory controls operation of both the first and second R/W circuits in a time division approach to stagger respective peak current intervals for the first and second mats.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: March 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dae-Seok Byeon
  • FLASH MEMORY DEVICE AND PROGRAM METHOD OF FLASH MEMORY DEVICE USING DIFFERENT VOLTAGES
    Publication number: 20110044108
    Abstract: A flash memory and a program method of the flash memory include applying a pass voltage to word lines to boost a channel voltage, which is discharged to a ground voltage. A program voltage is applied to a selected word line and a local voltage is applied to at least one word line supplied with the pass voltage while the program voltage is being applied to the selected word line. The local voltage is lower than the pass voltage and equal to or higher than the ground voltage. The boosted channel voltage may be discharged before the program voltage is applied to the selected word line.
    Type: Application
    Filed: November 4, 2010
    Publication date: February 24, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Seok Byeon, Young-Ho Lim
  • Flash memory device and program method of flash memory device using different voltages
    Patent number: 7852682
    Abstract: A flash memory and a program method of the flash memory include applying a pass voltage to word lines to boost a channel voltage, which is discharged to a ground voltage. A program voltage is applied to a selected word line and a local voltage is applied to at least one word line supplied with the pass voltage while the program voltage is being applied to the selected word line. The local voltage is lower than the pass voltage and equal to or higher than the ground voltage. The boosted channel voltage may be discharged before the program voltage is applied to the selected word line.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: December 14, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Seok Byeon, Young-Ho Lim
  • FLASH MEMORY DEVICE OPERATING AT MULTIPLE SPEEDS
    Publication number: 20100302869
    Abstract: A method of operating a flash memory device includes a first operating mode and a second operating mode having different operating speeds. Each one of the first and second operating modes includes a bit line set-up interval and at least one additional interval. The flash memory is divided into first and second mats connected to respective first and second R/W circuits. During the bit line set-up interval of the second operating mode, the flash memory controls operation of both the first and second R/W circuits in a time division approach to stagger respective peak current intervals for the first and second mats.
    Type: Application
    Filed: August 12, 2010
    Publication date: December 2, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Dae-Seok Byeon
  • Multi-chip package flash memory device and method for reading status data therefrom
    Patent number: 7843758
    Abstract: A method for reading status data from a multi-chip memory device including pluralities of memory chips is comprised of: providing a command to request an output of the status data to the plurality of memory chips; and accepting the status data of the plurality of memory chips through multiple channels of the multi-chip memory device. The reading method of the status data is helpful to shortening a standby time for accepting the status data of the multi-chip memory device, enhancing an operation rate.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: November 30, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dae-Seok Byeon
  • FLASH MEMORY DEVICE AND METHOD OF CONTROLLING FLASH MEMORY DEVICE
    Publication number: 20100259982
    Abstract: A flash memory device includes multiple memory blocks, a decoder configured to select at least one of the memory blocks in response to block select signals, a controller configured to generate the block select signals in response to a block address and to generate a flag signal when the block address corresponds to a bad block, and an output buffer configured to output fixed data in response to the flag signal indicating that the block address corresponds to the bad block. When the block address corresponds to a bad block, the controller generates the block select signals to cause the decoder to interrupt selection of a memory block corresponding to the block address.
    Type: Application
    Filed: June 24, 2010
    Publication date: October 14, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Seok Byeon, Young-Ho Lim
  • Flash memory devices and methods of programming the same by overlapping programming operations for multiple mats
    Patent number: 7800971
    Abstract: A flash memory device is programmed by loading first data into a page buffer of a first mat. Second data is loaded into a page buffer of a second mat while programming the first data in a first memory block of the first mat.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: September 21, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Sung Park, Dae-Seok Byeon
  • NON-VOLATILE MEMORY DEVICE AND SYSTEM HAVING REDUCED BIT LINE BIAS TIME
    Publication number: 20100202216
    Abstract: A non-volatile memory device and system are provided. The non-volatile memory device including; a memory cell array of memory blocks, and a bit line bias block connected to the bit lines and configured to precharge the bit lines, a page buffer precharging the plurality of bit lines and sensing data stored in the memory block via the bit lines, and a controller controlling the bit line bias block to simultaneously precharge the bit lines with the page buffer, thereby reducing the bit line bias time.
    Type: Application
    Filed: February 1, 2010
    Publication date: August 12, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Dae Seok BYEON