Patents by Inventor Daisuke Iwai

Daisuke Iwai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210081120
    Abstract: According to one embodiment, an electronic device connectable to a host via an interface includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory and capable of processing commands issued by the host in parallel. When the electronic device is connected to the host, the controller determines, when one or more commands to be processed by one or more deadline times, respectively, are issued by the host, scheduling indicative of timings at which the one or more commands are processed, respectively, based on the one or more deadline times. The controller performs processing corresponding to the one or more commands in accordance with the scheduling.
    Type: Application
    Filed: December 1, 2020
    Publication date: March 18, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Daisuke IWAI, Kenichiro YOSHII, Tetsuya SUNATA
  • Publication number: 20210072923
    Abstract: According to one embodiment, a storage device includes a nonvolatile memory including a plurality of blocks, and a controller. The controller receives from the host information indicative of the total number of processes running on the host. The controller executes processing of moving data stored in at least one block of the nonvolatile memory to at least one block of the other blocks of the nonvolatile memory, after determining that the total number of processes exceeds a first threshold value.
    Type: Application
    Filed: November 18, 2020
    Publication date: March 11, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Kenichiro YOSHII, Daisuke IWAI, Tetsuya SUNATA
  • Publication number: 20210064524
    Abstract: A memory system includes a first memory that is nonvolatile, a second memory that is volatile, and a memory controller. The memory controller is configured to store first information in the second memory. The first information includes management information. The memory controller is further configured to compress the first information. The compressed first information is second information. The memory controller is configured to store the second information in the first memory.
    Type: Application
    Filed: March 2, 2020
    Publication date: March 4, 2021
    Applicant: KIOXIA CORPORATION
    Inventors: Keiri NAKANISHI, Konosuke WATANABE, Kohei OIKAWA, Daisuke IWAI
  • Patent number: 10936203
    Abstract: A memory device can be connected to a host through an interface. The memory device includes a nonvolatile memory which includes a plurality of blocks, and a controller which is electrically connected to the nonvolatile memory. In a case where a read command is received from the host, the controller reads first data designated by the read command from a first block of the nonvolatile memory, to transmit the first data to the host, and to write the first data to a second block of the nonvolatile memory instead of the first block.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: March 2, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tetsuya Sunata, Daisuke Iwai, Kenichiro Yoshii
  • Patent number: 10891061
    Abstract: According to one embodiment, an electronic device connectable to a host via an interface includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory and capable of processing commands issued by the host in parallel. When the electronic device is connected to the host, the controller determines, when one or more commands to be processed by one or more deadline times, respectively, are issued by the host, scheduling indicative of timings at which the one or more commands are processed, respectively, based on the one or more deadline times. The controller performs processing corresponding to the one or more commands in accordance with the scheduling.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: January 12, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Daisuke Iwai, Kenichiro Yoshii, Tetsuya Sunata
  • Patent number: 10871920
    Abstract: According to one embodiment, a storage device includes a nonvolatile memory including a plurality of blocks, and a controller. The controller receives from the host information indicative of the total number of processes running on the host. The controller executes processing of moving data stored in at least one block of the nonvolatile memory to at least one block of the other blocks of the nonvolatile memory, after determining that the total number of processes exceeds a first threshold value.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: December 22, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Kenichiro Yoshii, Daisuke Iwai, Tetsuya Sunata
  • Publication number: 20200334145
    Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The nonvolatile memory cannot overwrite data written in a memory area. The controller controls writing/reading of data to/from the nonvolatile memory in response to a request from a host device. The controller includes a garbage collection processor and a garbage collection controller. The garbage collection processor executes garbage collection to reuse a memory area on the nonvolatile memory in which unnecessary data remain. The garbage collection controller stops the garbage collection executed by the garbage collection processor when the storage device is in a loaded state equal to or less than a threshold value.
    Type: Application
    Filed: July 6, 2020
    Publication date: October 22, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Kenichiro YOSHII, Tetsuya Sunata, Daisuke Iwai
  • Patent number: 10747663
    Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The nonvolatile memory cannot overwrite data written in a memory area. The controller controls writing/reading of data to/from the nonvolatile memory in response to a request from a host device. The controller includes a garbage collection processor and a garbage collection controller. The garbage collection processor executes garbage collection to reuse a memory area on the nonvolatile memory in which unnecessary data remain. The garbage collection controller stops the garbage collection executed by the garbage collection processor when the storage device is in a loaded state equal to or less than a threshold value.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: August 18, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Kenichiro Yoshii, Tetsuya Sunata, Daisuke Iwai
  • Publication number: 20200167081
    Abstract: According to one embodiment, an electronic device includes a nonvolatile memory that includes blocks and a controller. The controller transmits information to the host. The information indicates a first logical address range corresponding to cold data stored in the nonvolatile memory, and a processing amount for turning a cold block that comprises the cold data into a block to which data is writable. The controller reads the cold data from the nonvolatile memory in accordance with a read command that is received from the host and designates the first logical address range, and transmits the read cold data to the host. The controller writes, to the nonvolatile memory, the cold data that is received with a write command designating the first logical address range from the host.
    Type: Application
    Filed: February 3, 2020
    Publication date: May 28, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Tetsuya SUNATA, Daisuke Iwai, Kenichiro Yoshii
  • Publication number: 20200089428
    Abstract: According to one embodiment, a storage device is accessible by an external device via an interface and includes a nonvolatile memory including one or more blocks, and a controller electrically connected to the nonvolatile memory. The controller receives from the external device a request and a notification indicating that a response performance of the request is to be lowered. In response to receiving the request and notification, the controller determines a response time longer than a processing time of the request, and executes a first performance lowering process that executes a block managing process of the nonvolatile memory by using an idle time which is a difference between the response time and the processing time of the request or executes a second performance lowering process that lowers the response performance so as to process the request by spending the response time.
    Type: Application
    Filed: March 1, 2019
    Publication date: March 19, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tetsuya SUNATA, Daisuke IWAI, Kenichiro YOSHII
  • Patent number: 10585590
    Abstract: According to one embodiment, an electronic device includes a nonvolatile memory that includes blocks and a controller. The controller transmits information to the host. The information indicates a first logical address range corresponding to cold data stored in the nonvolatile memory, and a processing amount for turning a cold block that comprises the cold data into a block to which data is writable. The controller reads the cold data from the nonvolatile memory in accordance with a read command that is received from the host and designates the first logical address range, and transmits the read cold data to the host. The controller writes, to the nonvolatile memory, the cold data that is received with a write command designating the first logical address range from the host.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: March 10, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Tetsuya Sunata, Daisuke Iwai, Kenichiro Yoshii
  • Publication number: 20190378655
    Abstract: A multilayer ceramic capacitor includes: a multilayer chip in which each of dielectric layers and each of internal electrode layers are alternately stacked and the internal electrode layers are alternately exposed to two end faces; and external electrodes formed on the two end faces; wherein: the external electrodes have a structure in which a plated layer is formed on a ground layer including Mo; and “M?0.003185×(Ew×Et)?0.5921 is satisfied when “Et” is a height from a bottom one of the internal electrode layers to a top one of the internal electrode layers, “Ew” is a width of the internal electrode layers in a direction in which side faces of the multilayer chip face with each other, and “M” is a Mo concentration (atm %) with respect to a main component ceramic of a total of the multilayer chip and the pair of external electrodes.
    Type: Application
    Filed: June 6, 2019
    Publication date: December 12, 2019
    Inventors: Daisuke IWAI, Atsuhiro YANAGISAWA, Yoshinori SHIBATA, Masumi ISHII, Takeshi NOSAKI, Hiroyuki MOTEKI
  • Patent number: 10488347
    Abstract: A defect classification method in accordance with the present invention uses two types of images output from the defect inspection device 150 (i.e., the first inspection image generated from a luminance signal sequentially output from a detector SE and the second inspection image generated from a difference of the signals from an adjacent portion in a region where the defect exists). The first inspection image includes information for discriminating unevenness of the defective shape. Also, while it is difficult to discriminate unevenness of the defective shape by the second inspection image, the second inspection image includes information on a luminance distribution emphasizing a defective section. The region of the defective section is extracted from the second inspection image to be applied to the first inspection image and thereby define an arithmetic processing area, and the image processing is performed within the arithmetic processing area to compute a feature amount.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: November 26, 2019
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Tsuneo Terasawa, Hiroshi Fukuda, Daisuke Iwai
  • Publication number: 20190331608
    Abstract: A defect classification method in accordance with the present invention uses two types of images output from the defect inspection device 150 (i.e., the first inspection image generated from a luminance signal sequentially output from a detector SE and the second inspection image generated from a difference of the signals from an adjacent portion in a region where the defect exists). The first inspection image includes information for discriminating unevenness of the defective shape. Also, while it is difficult to discriminate unevenness of the defective shape by the second inspection image, the second inspection image includes information on a luminance distribution emphasizing a defective section. The region of the defective section is extracted from the second inspection image to be applied to the first inspection image and thereby define an arithmetic processing area, and the image processing is performed within the arithmetic processing area to compute a feature amount.
    Type: Application
    Filed: April 23, 2019
    Publication date: October 31, 2019
    Applicant: Shin-Etsu Chemical Co., Ltd.
    Inventors: Tsuneo Terasawa, Hiroshi Fukuda, Daisuke Iwai
  • Publication number: 20190303289
    Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The nonvolatile memory cannot overwrite data written in a memory area. The controller controls writing/reading of data to/from the nonvolatile memory in response to a request from a host device. The controller includes a garbage collection processor and a garbage collection controller. The garbage collection processor executes garbage collection to reuse a memory area on the nonvolatile memory in which unnecessary data remain. The garbage collection controller stops the garbage collection executed by the garbage collection processor when the storage device is in a loaded state equal to or less than a threshold value.
    Type: Application
    Filed: September 10, 2018
    Publication date: October 3, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Kenichiro YOSHII, Tetsuya SUNATA, Daisuke IWAI
  • Publication number: 20190303024
    Abstract: According to one embodiment, an electronic device connectable to a host via an interface includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory and capable of processing commands issued by the host in parallel. When the electronic device is connected to the host, the controller determines, when one or more commands to be processed by one or more deadline times, respectively, are issued by the host, scheduling indicative of timings at which the one or more commands are processed, respectively, based on the one or more deadline times. The controller performs processing corresponding to the one or more commands in accordance with the scheduling.
    Type: Application
    Filed: August 2, 2018
    Publication date: October 3, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Daisuke IWAI, Kenichiro Yoshii, Tetsuya Sunata
  • Publication number: 20190303019
    Abstract: A memory device can be connected to a host through an interface. The memory device includes a nonvolatile memory which includes a plurality of blocks, and a controller which is electrically connected to the nonvolatile memory. In a case where a read command is received from the host, the controller reads first data designated by the read command from a first block of the nonvolatile memory, to transmit the first data to the host, and to write the first data to a second block of the nonvolatile memory instead of the first block.
    Type: Application
    Filed: September 10, 2018
    Publication date: October 3, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Tetsuya SUNATA, Daisuke IWAI, Kenichiro YOSHII
  • Publication number: 20190294341
    Abstract: According to one embodiment, an electronic device includes a nonvolatile memory that includes blocks and a controller. The controller transmits information to the host. The information indicates a first logical address range corresponding to cold data stored in the nonvolatile memory, and a processing amount for turning a cold block that comprises the cold data into a block to which data is writable. The controller reads the cold data from the nonvolatile memory in accordance with a read command that is received from the host and designates the first logical address range, and transmits the read cold data to the host. The controller writes, to the nonvolatile memory, the cold data that is received with a write command designating the first logical address range from the host.
    Type: Application
    Filed: September 10, 2018
    Publication date: September 26, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Tetsuya SUNATA, Daisuke IWAI, Kenichiro YOSHII
  • Publication number: 20190294365
    Abstract: According to one embodiment, a storage device includes a nonvolatile memory including a plurality of blocks, and a controller. The controller receives from the host information indicative of the total number of processes running on the host. The controller executes processing of moving data stored in at least one block of the nonvolatile memory to at least one block of the other blocks of the nonvolatile memory, after determining that the total number of processes exceeds a first threshold value.
    Type: Application
    Filed: July 27, 2018
    Publication date: September 26, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Kenichiro YOSHII, Daisuke IWAI, Tetsuya SUNATA
  • Publication number: 20190244758
    Abstract: A multilayer ceramic capacitor includes: a ceramic multilayer structure having a structure in which each of ceramic dielectric layers and each of internal electrode layers are alternately stacked and are alternately exposed to two edge faces of the ceramic multilayer structure, a main phase of the plurality of ceramic dielectric layers having a perovskite structure that includes Ca and Zr and is expressed by a general formula ABO3; and a pair of external electrodes that are formed on the two edge faces, wherein 300×TE/TA?12?30 is satisfied when a volume TA is a length CL×a width CW×a thickness CT of the ceramic multilayer structure and a volume TE is a length EL×a width EW×a thickness ET×a stacked number of the plurality of internal electrode layers in a capacity region.
    Type: Application
    Filed: January 28, 2019
    Publication date: August 8, 2019
    Inventors: Michio OSHIMA, Atsuhiro YANAGISAWA, Yoshinori SHIBATA, Daisuke IWAI, Hiroyuki MOTEKI