Abstract: A ceramic electronic component includes: a ceramic body including main surfaces perpendicular to a first axis and end surfaces perpendicular to a second axis; and external electrodes covering the end surfaces and extending from the end surfaces to the main surfaces. The external electrode includes a surface layer portion including a Sn plating layer, and an inner layer portion including a Ni plating layer adjacent to the Sn plating layer and including rounded inner end portions on the main surfaces. In a cross-section perpendicular to a third axis, a ratio t2/t1 is 0.4 or more, where t2 is a thickness in the first axis direction of a portion where an inclination of a tangent line of an outer surface of the inner end portion to each main surface is 45°, and t1 is a maximum thickness in the first axis direction of the inner layer portion on each main surface.

Abstract: A ceramic electronic component includes: a ceramic body including main surfaces perpendicular to a first axis and end surfaces perpendicular to a second axis; and external electrodes covering the end surfaces and extending from the end surfaces to the main surfaces. The external electrode includes a surface layer portion including a Sn plating layer, and an inner layer portion including a Ni plating layer adjacent to the Sn plating layer and including rounded inner end portions on the main surfaces. In a cross-section perpendicular to a third axis, a ratio t2/t1 is 0.4 or more, where t2 is a thickness in the first axis direction of a portion where an inclination of a tangent line of an outer surface of the inner end portion to each main surface is 45°, and t1 is a maximum thickness in the first axis direction of the inner layer portion on each main surface.

Abstract: A multi-layer ceramic electronic component includes a ceramic body and an external electrode. The ceramic body includes a plurality of internal electrodes laminated in one axial direction, and an end surface extending along a plane parallel to the axial direction, at least part of the plurality of internal electrode being drawn from the end surface. The external electrode covers the end surface of the ceramic body. In a thermal desorption spectrum of water of the multi-layer ceramic electronic component by thermal desorption spectroscopy, a ratio P1/P2 of a detection intensity P1 of a first peak in a range of 200° C. to 300° C. to a detection intensity P2 of a second peak in a range of 550° C. to 800° C. is equal to or lower than 11.

Abstract: According to one embodiment, a nonvolatile memory includes a memory chip and a command processing unit. The command processing unit stores data read from a first position of the memory chip in a memory when a first command for compaction is received from a controller, transmits validity determination information used for determining whether or not the data read from the first position is valid to the controller, and writes valid data of the data stored in the memory to a second position of the memory chip when a second command for the compaction and validity identification information that identifies the valid data are received from the controller.

Abstract: According to one embodiment, a nonvolatile memory includes a memory chip and a command processing unit. The command processing unit stores data read from a first position of the memory chip in a memory when a first command for compaction is received from a controller, transmits validity determination information used for determining whether or not the data read from the first position is valid to the controller, and writes valid data of the data stored in the memory to a second position of the memory chip when a second command for the compaction and validity identification information that identifies the valid data are received from the controller.

Abstract: According to one embodiment, an electronic device includes a nonvolatile memory that includes blocks and a controller. The controller transmits information to the host. The information indicates a first logical address range corresponding to cold data stored in the nonvolatile memory, and a processing amount for turning a cold block that comprises the cold data into a block to which data is writable. The controller reads the cold data from the nonvolatile memory in accordance with a read command that is received from the host and designates the first logical address range, and transmits the read cold data to the host. The controller writes, to the nonvolatile memory, the cold data that is received with a write command designating the first logical address range from the host.

Abstract: A ceramic electronic component includes: a ceramic body including main surfaces perpendicular to a first axis and end surfaces perpendicular to a second axis; and external electrodes covering the end surfaces and extending from the end surfaces to the main surfaces. The external electrode includes a surface layer portion including a Sn plating layer, and an inner layer portion including a Ni plating layer adjacent to the Sn plating layer and including rounded inner end portions on the main surfaces. In a cross-section perpendicular to a third axis, a ratio t2/t1 is 0.4 or more, where t2 is a thickness in the first axis direction of a portion where an inclination of a tangent line of an outer surface of the inner end portion to each main surface is 45°, and t1 is a maximum thickness in the first axis direction of the inner layer portion on each main surface.

Abstract: A multi-layer ceramic electronic component includes a ceramic body and an external electrode. The ceramic body includes a plurality of internal electrodes laminated in one axial direction, and an end surface extending along a plane parallel to the axial direction, at least part of the plurality of internal electrode being drawn from the end surface. The external electrode covers the end surface of the ceramic body. In a thermal desorption spectrum of water of the multi-layer ceramic electronic component by thermal desorption spectroscopy, a ratio P1/P2 of a detection intensity P1 of a first peak in a range of 200° C. to 300° C. to a detection intensity P2 of a second peak in a range of 550° C. to 800° C. is equal to or lower than 11.

Abstract: A memory system includes a first memory that is nonvolatile, a second memory that is volatile, and a memory controller. The memory controller is configured to store first information in the second memory. The first information includes management information. The memory controller is further configured to compress the first information. The compressed first information is second information. The memory controller is configured to store the second information in the first memory.

Abstract: According to one embodiment, an electronic device connectable to a host via an interface includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory and capable of processing commands issued by the host in parallel. When the electronic device is connected to the host, the controller determines, when one or more commands to be processed by one or more deadline times, respectively, are issued by the host, scheduling indicative of timings at which the one or more commands are processed, respectively, based on the one or more deadline times. The controller performs processing corresponding to the one or more commands in accordance with the scheduling.

Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The nonvolatile memory cannot overwrite data written in a memory area. The controller controls writing/reading of data to/from the nonvolatile memory in response to a request from a host device. The controller includes a garbage collection processor and a garbage collection controller. The garbage collection processor executes garbage collection to reuse a memory area on the nonvolatile memory in which unnecessary data remain. The garbage collection controller stops the garbage collection executed by the garbage collection processor when the storage device is in a loaded state equal to or less than a threshold value.

Abstract: The present disclosure relates to a method for calibrating a projector. In one example, the method includes receiving by a processing element light field data corresponding to a calibration image projected by a projector and captured by a light field capturing device, and modeling by a processing element one or more intrinsic properties of the projector using the light field data and the calibration image. The calibration image may be projected by the projector directly into the light field capturing device.

Abstract: According to one embodiment, a storage device is accessible by an external device via an interface and includes a nonvolatile memory including one or more blocks, and a controller electrically connected to the nonvolatile memory. The controller receives from the external device a request and a notification indicating that a response performance of the request is to be lowered. In response to receiving the request and notification, the controller determines a response time longer than a processing time of the request, and executes a first performance lowering process that executes a block managing process of the nonvolatile memory by using an idle time which is a difference between the response time and the processing time of the request or executes a second performance lowering process that lowers the response performance so as to process the request by spending the response time.

Abstract: According to one embodiment, a nonvolatile memory includes a memory chip and a command processing unit. The command processing unit stores data read from a first position of the memory chip in a memory when a first command for compaction is received from a controller, transmits validity determination information used for determining whether or not the data read from the first position is valid to the controller, and writes valid data of the data stored in the memory to a second position of the memory chip when a second command for the compaction and validity identification information that identifies the valid data are received from the controller.

Abstract: A ceramic electronic component includes a multilayer chip including a multilayer structure having ceramic dielectric layers and internal electrode layers alternately stacked, and cover layers respectively disposed on top and bottom faces of the multilayer structure in a first direction in which the dielectric layers and the internal electrode layers are stacked, and a pair of external electrodes formed from respective edge faces to at least one side face of the multilayer chip, wherein a ratio of a thickness of the multilayer chip in the first direction to a width of the multilayer chip in a shorter side direction is 0.7 or less, wherein a thickness of a capacitance section where adjacent internal electrode layers connected to different external electrodes are opposite to each other in the first direction is equal to or greater than 2.2 times at least one of thicknesses of the cover layers in the first direction.

Abstract: According to one embodiment, an electronic device includes a nonvolatile memory that includes blocks and a controller. The controller transmits information to the host. The information indicates a first logical address range corresponding to cold data stored in the nonvolatile memory, and a processing amount for turning a cold block that comprises the cold data into a block to which data is writable. The controller reads the cold data from the nonvolatile memory in accordance with a read command that is received from the host and designates the first logical address range, and transmits the read cold data to the host. The controller writes, to the nonvolatile memory, the cold data that is received with a write command designating the first logical address range from the host.

Abstract: According to one embodiment, an electronic device includes a nonvolatile memory that includes blocks and a controller. The controller transmits information to the host. The information indicates a first logical address range corresponding to cold data stored in the nonvolatile memory, and a processing amount for turning a cold block that comprises the cold data into a block to which data is writable. The controller reads the cold data from the nonvolatile memory in accordance with a read command that is received from the host and designates the first logical address range, and transmits the read cold data to the host. The controller writes, to the nonvolatile memory, the cold data that is received with a write command designating the first logical address range from the host.

Abstract: A multilayer ceramic capacitor includes: a multilayer chip in which each of dielectric layers and each of internal electrode layers are alternately stacked and the internal electrode layers are alternately exposed to two end faces; and external electrodes formed on the two end faces; wherein: the external electrodes have a structure in which a plated layer is formed on a ground layer including Mo; and “M?0.003185×(Ew×Et)?0.5921 is satisfied when “Et” is a height from a bottom one of the internal electrode layers to a top one of the internal electrode layers, “Ew” is a width of the internal electrode layers in a direction in which side faces of the multilayer chip face with each other, and “M” is a Mo concentration (atm %) with respect to a main component ceramic of a total of the multilayer chip and the pair of external electrodes.

Abstract: A multilayer ceramic capacitor includes: a ceramic multilayer structure having a structure in which each of ceramic dielectric layers and each of internal electrode layers are alternately stacked and are alternately exposed to two edge faces of the ceramic multilayer structure, a main phase of the plurality of ceramic dielectric layers having a perovskite structure that includes Ca and Zr and is expressed by a general formula ABO3; and a pair of external electrodes that are formed on the two edge faces, wherein 300×TE/TA?12?30 is satisfied when a volume TA is a length CL×a width CW×a thickness CT of the ceramic multilayer structure and a volume TE is a length EL×a width EW×a thickness ET×a stacked number of the plurality of internal electrode layers in a capacity region.