Patents by Inventor Dale W. Collins
Dale W. Collins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240045604Abstract: Methods, systems, and devices for self-aligned techniques for forming connections in a memory device are described. A redistribution layer (RDL) for coupling an electrode of a capacitor of a memory cell with a corresponding selector device may be fabricated at a same time or stage as the electrode, using self-aligned techniques. When forming portions of a memory cell, a cavity for the electrode may be etched, and a portion of the RDL that extends from the electrode cavity to a corresponding selector device may also be selectively etched. The resulting cavities may be filled with an electrode material, which may form the electrode and couple the electrode to the corresponding selector device. The resulting memory device may support implementation of a staggered configuration for memory cells, and may include electrodes that share a crystalline structure with one or more corresponding portions of an RDL.Type: ApplicationFiled: August 2, 2022Publication date: February 8, 2024Inventors: Zhuo Chen, Beth R. Cook, Dale W. Collins, Muralikrishnan Balakrishnan
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Publication number: 20230270025Abstract: Methods, systems, and devices for chalcogenide memory device compositions are described. A memory cell may use a chalcogenide material having a composition as described herein as a storage materials, a selector materials, or as a self-selecting storage material. A chalcogenide material as described herein may include a sulfurous component, which may be completely sulfur (S) or may be a combination of sulfur and one or more other elements, such as selenium (Se). In addition to the sulfurous component, the chalcogenide material may further include one or more other elements, such as germanium (Ge), at least one Group-III element, or arsenic (As).Type: ApplicationFiled: February 21, 2022Publication date: August 24, 2023Inventors: Dale W. Collins, Paolo Fantini, Lorenzo Fratin, Enrico Varesi
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Patent number: 11641788Abstract: Methods, systems, and devices for a resistive interface material are described. A memory device may be fabricated using a sequence of steps that include forming a stack of materials by depositing a first metal layer, depositing a first electrode layer on the metal layer, depositing a memory material on the first electrode layer to form one or more memory cells, depositing a second electrode layer on the memory material, and depositing a second metal layer on the second electrode layer. A lamina (or multiple) having a relatively high resistivity may be included in the stack of materials to reduce or eliminate a current spike that may otherwise occur across the memory cells during an access operation.Type: GrantFiled: December 9, 2020Date of Patent: May 2, 2023Assignee: Micron Technology, Inc.Inventors: Andrea Gotti, Dale W. Collins, Fabio Pellizzer
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Publication number: 20230113573Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.Type: ApplicationFiled: October 21, 2022Publication date: April 13, 2023Inventors: Trupti D. Gawai, David S. Pratt, Ahmed M. Elsied, David A. Kewley, Dale W. Collins, Raju Ahmed, Chelsea M. Jordan, Radhakrishna Kotti
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Patent number: 11575085Abstract: Methods, systems, and devices for techniques for forming memory structures are described. Forming a memory structure may include etching a stack of material including a conductive line, a first electrode and a sacrificial material to divide the stack of material into multiple sections. The process may further include depositing an oxide material in each of the first quantity of channels to form multiple oxide materials. The sacrificial material may be etched to form a second channel between two oxide materials of the multiple oxide materials. Memory material may be deposited over the two oxide materials and the second channel, which may create a void in the second channel between the memory material and the first electrode. The memory material may be heated to fill the void in the second channel.Type: GrantFiled: February 2, 2021Date of Patent: February 7, 2023Assignee: Micron Technology, Inc.Inventors: Andrea Gotti, Pavan Reddy K. Aella, Dale W. Collins
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Patent number: 11515204Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.Type: GrantFiled: December 29, 2020Date of Patent: November 29, 2022Assignee: Micron Technology, Inc.Inventors: Trupti D. Gawai, David S. Pratt, Ahmed M. Elsied, David A. Kewley, Dale W. Collins, Raju Ahmed, Chelsea M. Jordan, Radhakrishna Kotti
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Publication number: 20220208606Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.Type: ApplicationFiled: December 29, 2020Publication date: June 30, 2022Inventors: Trupti D. Gawai, David S. Pratt, Ahmed M. Elsied, David A. Kewley, Dale W. Collins, Raju Ahmed, Chelsea M. Jordan, Radhakrishna Kotti
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Publication number: 20220181549Abstract: Methods, systems, and devices for a resistive interface material are described. A memory device may be fabricated using a sequence of steps that include forming a stack of materials by depositing a first metal layer, depositing a first electrode layer on the metal layer, depositing a memory material on the first electrode layer to form one or more memory cells, depositing a second electrode layer on the memory material, and depositing a second metal layer on the second electrode layer. A lamina (or multiple) having a relatively high resistivity may be included in the stack of materials to reduce or eliminate a current spike that may otherwise occur across the memory cells during an access operation.Type: ApplicationFiled: December 9, 2020Publication date: June 9, 2022Inventors: Andrea Gotti, Dale W. Collins, Fabio Pellizzer
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Publication number: 20210234097Abstract: Methods, systems, and devices for techniques for forming memory structures are described. Forming a memory structure may include etching a stack of material including a conductive line, a first electrode and a sacrificial material to divide the stack of material into multiple sections. The process may further include depositing an oxide material in each of the first quantity of channels to form multiple oxide materials. The sacrificial material may be etched to form a second channel between two oxide materials of the multiple oxide materials. Memory material may be deposited over the two oxide materials and the second channel, which may create a void in the second channel between the memory material and the first electrode. The memory material may be heated to fill the void in the second channel.Type: ApplicationFiled: February 2, 2021Publication date: July 29, 2021Inventors: Andrea Gotti, Pavan Reddy K. Aella, Dale W. Collins
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Patent number: 11038107Abstract: A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. Related semiconductor devices and systems, methods of forming the semiconductor structure, semiconductor device, and systems, and methods of forming the liner in situ are disclosed.Type: GrantFiled: November 28, 2018Date of Patent: June 15, 2021Assignee: Micron Technology, Inc.Inventors: Dale W. Collins, Andrea Gotti, F. Daniel Gealy, Tuman E. Allen, Swapnil Lengade
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Patent number: 10930849Abstract: Methods, systems, and devices for techniques for forming memory structures are described. Forming a memory structure may include etching a stack of material including a conductive line, a first electrode and a sacrificial material to divide the stack of material into multiple sections. The process may further include depositing an oxide material in each of the first quantity of channels to form multiple oxide materials. The sacrificial material may be etched to form a second channel between two oxide materials of the multiple oxide materials. Memory material may be deposited over the two oxide materials and the second channel, which may create a void in the second channel between the memory material and the first electrode. The memory material may be heated to fill the void in the second channel.Type: GrantFiled: June 28, 2019Date of Patent: February 23, 2021Assignee: Micron Technology, Inc.Inventors: Andrea Gotti, Pavan Reddy K. Aella, Dale W. Collins
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Publication number: 20200411761Abstract: Methods, systems, and devices for techniques for forming memory structures are described. Forming a memory structure may include etching a stack of material including a conductive line, a first electrode and a sacrificial material to divide the stack of material into multiple sections. The process may further include depositing an oxide material in each of the first quantity of channels to form multiple oxide materials. The sacrificial material may be etched to form a second channel between two oxide materials of the multiple oxide materials. Memory material may be deposited over the two oxide materials and the second channel, which may create a void in the second channel between the memory material and the first electrode. The memory material may be heated to fill the void in the second channel.Type: ApplicationFiled: June 28, 2019Publication date: December 31, 2020Inventors: Andrea Gotti, Pavan Reddy K. Aella, Dale W. Collins
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Patent number: 10879113Abstract: Some embodiments include methods for depositing copper-containing material utilizing physical vapor deposition of the copper-containing material while keeping a temperature of the deposited copper-containing material at greater than 100° C. Some embodiments include methods in which openings are lined with a metal-containing composition, copper-containing material is physical vapor deposited over the metal-containing composition while a temperature of the copper-containing material is no greater than about 0° C., and the copper-containing material is then annealed while the copper-containing material is at a temperature in a range of from about 180° C. to about 250° C. Some embodiments include methods in which openings are lined with a composition containing metal and nitrogen, and the lined openings are at least partially filled with copper-containing material.Type: GrantFiled: August 14, 2018Date of Patent: December 29, 2020Assignee: Micron Technology, Inc.Inventors: Dale W. Collins, Joe Lindgren
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Patent number: 10347831Abstract: Doping a storage element, a selector element, or both, of a memory cell with a dopant including one or more of aluminum (Al), zirconium (Zr), hafnium (Hf), and silicon (Si), can minimize volume or density changes in a phase change memory as well as minimize electromigration, in accordance with embodiments. In one embodiment, a memory cell includes a first electrode and a second electrode, and a storage element comprising a layer of doped phase change material between the first and second electrodes, wherein the doped phase change material includes one or more of aluminum, zirconium, hafnium, and silicon. The storage element, a selector element, or both can be doped using techniques such as cosputtering or deposition of alternating layers of a dopant layer and a storage (or selector) material.Type: GrantFiled: June 13, 2018Date of Patent: July 9, 2019Assignee: Intel CorporationInventors: Daniel Gealy, Andrea Gotti, Dale W. Collins, Swapnil A. Lengade
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Patent number: 10256406Abstract: A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. Related semiconductor devices and systems, methods of forming the semiconductor structure, semiconductor device, and systems, and methods of forming the liner in situ are disclosed.Type: GrantFiled: May 16, 2016Date of Patent: April 9, 2019Assignee: Micron Technology, Inc.Inventors: Dale W. Collins, Andrea Gotti, F. Daniel Gealy, Tuman E. Allen, Swapnil Lengade
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Publication number: 20190097133Abstract: A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. Related semiconductor devices and systems, methods of forming the semiconductor structure, semiconductor device, and systems, and methods of forming the liner in situ are disclosed.Type: ApplicationFiled: November 28, 2018Publication date: March 28, 2019Inventors: Dale W. Collins, Andrea Gotti, F. Daniel Gealy, Tuman E. Allen, Swapnil Lengade
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Publication number: 20180374745Abstract: Some embodiments include methods for depositing copper-containing material utilizing physical vapor deposition of the copper-containing material while keeping a temperature of the deposited copper-containing material at greater than 100° C. Some embodiments include methods in which openings are lined with a metal-containing composition, copper-containing material is physical vapor deposited over the metal-containing composition while a temperature of the copper-containing material is no greater than about 0° C., and the copper-containing material is then annealed while the copper-containing material is at a temperature in a range of from about 180° C. to about 250° C. Some embodiments include methods in which openings are lined with a composition containing metal and nitrogen, and the lined openings are at least partially filled with copper-containing material.Type: ApplicationFiled: August 14, 2018Publication date: December 27, 2018Applicant: Micron Technology, Inc.Inventors: Dale W. Collins, Joe Lindgren
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Publication number: 20180337329Abstract: Doping a storage element, a selector element, or both, of a memory cell with a dopant including one or more of aluminum (Al), zirconium (Zr), hafnium (Hf), and silicon (Si), can minimize volume or density changes in a phase change memory as well as minimize electromigration, in accordance with embodiments. In one embodiment, a memory cell includes a first electrode and a second electrode, and a storage element comprising a layer of doped phase change material between the first and second electrodes, wherein the doped phase change material includes one or more of aluminum, zirconium, hafnium, and silicon. The storage element, a selector element, or both can be doped using techniques such as cosputtering or deposition of alternating layers of a dopant layer and a storage (or selector) material.Type: ApplicationFiled: June 13, 2018Publication date: November 22, 2018Inventors: Daniel GEALY, Andrea GOTTI, Dale W. COLLINS, Swapnil A. LENGADE
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Patent number: 10121697Abstract: Some embodiments include methods for depositing copper-containing material utilizing physical vapor deposition of the copper-containing material while keeping a temperature of the deposited copper-containing material at greater than 100° C. Some embodiments include methods in which openings are lined with a metal-containing composition, copper-containing material is physical vapor deposited over the metal-containing composition while a temperature of the copper-containing material is no greater than about 0° C., and the copper-containing material is then annealed while the copper-containing material is at a temperature in a range of from about 180° C. to about 250° C. Some embodiments include methods in which openings are lined with a composition containing metal and nitrogen, and the lined openings are at least partially filled with copper-containing material.Type: GrantFiled: November 2, 2015Date of Patent: November 6, 2018Assignee: Micron Technology, Inc.Inventors: Dale W. Collins, Joe Lindgren
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Patent number: 10090462Abstract: Electronic apparatus, systems, and methods can include a resistive memory cell having a structured as an operably variable resistance region between two electrodes and a metallic barrier disposed in a region between the dielectric and one of the two electrodes. The metallic barrier can have a structure and a material composition to provide oxygen diffusivity above a first threshold during program or erase operations of the resistive memory cell and oxygen diffusivity below a second threshold during a retention state of the resistive memory cell. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: December 7, 2015Date of Patent: October 2, 2018Assignee: Micron Technology, Inc.Inventors: Durai Vishak Nirmal Ramaswamy, Lei Bi, Beth R. Cook, Dale W. Collins