Patents by Inventor Dale W. Collins

Dale W. Collins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7375014
    Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: May 20, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Dale W. Collins, Richard H. Lane, Rita J. Klein
  • Patent number: 7348234
    Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: March 25, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Dale W. Collins, Richard H. Lane, Rita J. Klein
  • Patent number: 7344977
    Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: March 18, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Dale W. Collins, Richard H. Lane, Rita J. Klein
  • Patent number: 7335981
    Abstract: Methods are provided for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are deposited on the wall of the via, reacting with the surface of the wall until the entire wall is covered by the lining material. The lining material is then fixed in place to form a layer lining the via. The lined via may then be filled with a desired material. For example, a via lined with an insulative material may be filled with a material such as copper to create an insulated conductive via through the substrate.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: February 26, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Dale W. Collins, Steven M. McDonald
  • Publication number: 20080041725
    Abstract: An electrolyte solution, methods, and systems for selectively removing a conductive metal from a substrate are provided. The electrolyte solution comprising nanoparticles that are more noble than the conductive metal being removed, is applied to a substrate to remove the conductive metal selectively relative to a dielectric material without application of an external potential or contact of a processing pad with the surface of the substrate. The solutions and methods can be applied, for example, to remove a conductive metal layer (e.g., barrier metal) selectively relative to dielectric material and to a materially different conductive metal (e.g., copper interconnect) without application of an external potential or contact of a processing pad with the surface of the substrate.
    Type: Application
    Filed: August 21, 2006
    Publication date: February 21, 2008
    Applicant: Micron Technology, Inc.
    Inventors: Rita J. Klein, Dale W. Collins, Paul Morgan, Joseph N. Greeley, Nishant Sinha
  • Patent number: 7282131
    Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: October 16, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Dale W. Collins, Richard H. Lane, Rita J. Klein
  • Patent number: 7273778
    Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: September 25, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Dale W. Collins, Richard H. Lane, Rita J. Klein
  • Patent number: 7192495
    Abstract: The present teachings and illustrations describe a process for forming a plurality of conductive structures in or on a substrate. In one embodiment, the process comprises forming a plurality of recesses in or on the substrate, wherein the plurality of recesses include recesses having different dimensions. In addition, the process further comprises (i) forming a conductive layer which at least partially fills the plurality of recesses and (ii) treating the conductive layer to improve the conductive properties of the conductive layer. Moreover, the process still further comprises (iii) sequentially repeating acts (i) and (ii) until each of the recesses of the plurality of recesses are filled to a desired dimension and such that the conductive material in the recesses of smaller dimension are more uniformly adhered to the bottom surfaces of the recesses.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: March 20, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Dale W. Collins
  • Patent number: 7179361
    Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: February 20, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Dale W. Collins, Richard H. Lane, Rita J. Klein
  • Patent number: 7179716
    Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: February 20, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Dale W. Collins, Richard H. Lane, Rita J. Klein
  • Patent number: 7105921
    Abstract: Methods are provided for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are deposited on the wall of the via, reacting with the surface of the wall until the entire wall is covered by the lining material. The lining material is then fixed in place to form a layer lining the via. The lined via may then be filled with a desired material. For example, a via lined with an insulative material may be filled with a material such as copper to create an insulated conductive via through the substrate.
    Type: Grant
    Filed: October 10, 2005
    Date of Patent: September 12, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Dale W. Collins, Steven M. McDonald
  • Patent number: 7105437
    Abstract: Methods are provided for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are deposited on the wall of the via, reacting with the surface of the wall until the entire wall is covered by the lining material. The lining material is then fixed in place to form a layer lining the via. The lined via may then be filled with a desired material. For example, a via lined with an insulative material may be filled with a material such as copper to create an insulated conductive via through the substrate.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: September 12, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Dale W. Collins, Steven M. McDonald
  • Patent number: 7098128
    Abstract: Methods of electroless filling electrically different features such as contact openings to form interconnects and conductive contacts, and semiconductor devices, dies, and systems that incorporate the interconnects and contacts are disclosed. The contact openings are electrically shorted together with a selective material, a nucleation layer is selectively deposited onto the area to be plated (e.g., the base of the opening), and a conductive material is electroless plated onto the nucleation layer to fill the opening. The process achieves substantially simultaneous filling of openings having different surface potentials at an about even rate.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: August 29, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Dale W Collins, Rita J Klein
  • Patent number: 7030010
    Abstract: Methods for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are deposited on the wall of the via, reacting with the surface of the wall until the entire wall is covered by the lining material. The lining material is then fixed in place to form a layer lining the via. The lined via may then be filled with a desired material. For example, a via lined with an insulative material may be filled with a material such as copper to create an insulated conductive via through the substrate.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: April 18, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Dale W. Collins, Steven M. McDonald
  • Patent number: 7025866
    Abstract: Methods for forming microelectronic workpieces used in electrochemical deposition processes, methods of depositing a conductive layer on a microelectronic workpiece, and articles for electrochemical deposition in semiconductor fabrication. One aspect of the invention is directed toward methods for forming microelectronic workpieces that are well-suited for electrochemical deposition processes. On embodiment of such a method comprises depositing a first conductive material on a workpiece to form an electrically conductive first layer that conforms to the workpiece. This embodiment further includes forming a seed region defined by a second layer of a second conductive material on the first layer, and forming a contact region defined by an exposed portion of the first layer that is not covered by the second layer. The contact region can extend around at least a portion of the perimeter of the workpiece.
    Type: Grant
    Filed: August 21, 2002
    Date of Patent: April 11, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Dale W. Collins
  • Patent number: 7001492
    Abstract: A method of electroplating metal onto a low conductivity layer combines a potential or current reversal waveform with variation in the amplitude and duration of the applied potential or current pulse. The method includes, over time, varying the duration of the pulse and continuously decreasing the amplitude of both the cathodic and anodic portions of the waveform across the surface of the low conductivity layer as the deposition zone moves from the center of the surface of the low conductivity layer to the outside edge. By virtue of the ability to vary the amplitude and duration of the pulse, the method facilitates the filling of structures in the center of the low conductivity layer without overdepositing on the outside edge, thus ensuring a controlled deposition of material across the surface of the low conductivity layer.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: February 21, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Dale W. Collins
  • Patent number: 6984301
    Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: January 10, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Dale W. Collins, Richard H. Lane, Rita J. Klein
  • Patent number: 6723219
    Abstract: A method of electroplating metal onto a low conductivity layer combines a potential or current reversal waveform with variation in the amplitude and duration of the applied potential or current pulse. The method includes, over time, varying the duration of the pulse and continuously decreasing the amplitude of both the cathodic and anodic portions of the waveform across the surface of the low conductivity layer as the deposition zone moves from the center of the surface of the low conductivity layer to the outside edge. By virtue of the ability to vary the amplitude and duration of the pulse, the method facilitates the filling of structures in the center of the low conductivity layer without overdepositing on the outside edge, thus ensuring a controlled deposition of material across the surface of the low conductivity layer.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: April 20, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Dale W. Collins
  • Publication number: 20040043607
    Abstract: Methods for creating lined vias in semiconductor substrates. Using electrophoretic techniques deposit, micelles of a lining material are deposited on the walls of the via, reacting with the surface of the wall until the entire wall is covered by the lining material. The lining material is then fixed in place to form a layer lining the via. The lined via may then be filled with a desired material. For example a via lined with an insulative material may be filled with a material such as copper to create a insulated conductive via through the substrate.
    Type: Application
    Filed: August 29, 2002
    Publication date: March 4, 2004
    Inventors: Warren M. Farnworth, Dale W. Collins, Steven M. McDonald
  • Publication number: 20040038052
    Abstract: Methods for forming microelectronic workpieces used in electrochemical deposition processes, methods of depositing a conductive layer on a microelectronic workpiece, and articles for electrochemical deposition in semiconductor fabrication. One aspect of the invention is directed toward methods for forming microelectronic workpieces that are well-suited for electrochemical deposition processes. On embodiment of such a method comprises depositing a first conductive material on a workpiece to form an electrically conductive first layer that conforms to the workpiece. This embodiment further includes forming a seed region defined by a second layer of a second conductive material on the first layer, and forming a contact region defined by an exposed portion of the first layer that is not covered by the second layer. The contact region can extend around at least a portion of the perimeter of the workpiece.
    Type: Application
    Filed: August 21, 2002
    Publication date: February 26, 2004
    Inventor: Dale W. Collins