Patents by Inventor Dale W. Collins
Dale W. Collins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9006702Abstract: Semiconductor structures including a zirconium oxide material and methods of forming the same are described herein. As an example, a semiconductor structure can include a zirconium oxide material, a perovskite structure material, and a noble metal material formed between the zirconium oxide material and the perovskite structure material.Type: GrantFiled: January 20, 2014Date of Patent: April 14, 2015Assignee: Micron Technology, Inc.Inventors: Dale W. Collins, D. V. Nirmal Ramaswamy, Matthew N. Rocklein, Swapnil A. Lengade
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Publication number: 20150056798Abstract: Some embodiments include methods of forming memory cells. Metal oxide may be deposited over a first electrode, with the deposited metal oxide having a relatively low degree of crystallinity. The degree of crystallinity within the metal oxide may be increased after the deposition of the metal oxide. A dielectric material may be formed over the metal oxide, and a second electrode may be formed over the dielectric material. The degree of crystallinity may be increased with a thermal treatment. The thermal treatment may be conducted before, during, and/or after formation of the dielectric material.Type: ApplicationFiled: October 3, 2014Publication date: February 26, 2015Inventors: Noel Rocklein, Durai Ramaswamy, Dale W. Collins, Swapnil Lengade, Srividya Krishnamurthy, Mark S. Korber
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Patent number: 8859382Abstract: Some embodiments include methods of forming memory cells. Metal oxide may be deposited over a first electrode, with the deposited metal oxide having a relatively low degree of crystallinity. The degree of crystallinity within the metal oxide may be increased after the deposition of the metal oxide. A dielectric material may be formed over the metal oxide, and a second electrode may be formed over the dielectric material. The degree of crystallinity may be increased with a thermal treatment. The thermal treatment may be conducted before, during, and/or after formation of the dielectric material.Type: GrantFiled: October 26, 2011Date of Patent: October 14, 2014Assignee: Micron Technology, Inc.Inventors: Noel Rocklein, D. V. Nirmal Ramaswamy, Dale W. Collins, Swapnil Lengade, Srividya Krishnamurthy, Mark Korber
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Publication number: 20140268991Abstract: Embodiments disclosed herein may relate to a memory cell comprising a chalcogenide material mixture having a chalcogenide composition and a metallic glass-forming composition.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Yongjun J. Hu, Dale W. Collins, Everett A. McTeer
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Publication number: 20140191229Abstract: Semiconductor structures including a zirconium oxide material and methods of forming the same are described herein. As an example, a semiconductor structure can include a zirconium oxide material, a perovskite structure material, and a noble metal material formed between the zirconium oxide material and the perovskite structure material.Type: ApplicationFiled: January 20, 2014Publication date: July 10, 2014Applicant: Micron Technology, Inc.Inventors: Dale W. Collins, D.V. Nirmal Ramaswamy, Matthew N. Rocklein, Swapnil A. Lengade
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Publication number: 20140061568Abstract: Electronic apparatus, systems, and methods can include a resistive memory cell having a structured as an operably variable resistance region between two electrodes and a metallic barrier disposed in a region between the dielectric and one of the two electrodes. The metallic barrier can have a structure and a material composition to provide oxygen diffusivity above a first threshold during program or erase operations of the resistive memory cell and oxygen diffusivity below a second threshold during a retention state of the resistive memory cell. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: August 30, 2012Publication date: March 6, 2014Inventors: Durai Vishak Nirmal Ramaswamy, Lei Bi, Beth R. Cook, Dale W. Collins
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Patent number: 8637846Abstract: Semiconductor structures including a zirconium oxide material and methods of forming the same are described herein. As an example, a semiconductor structure can include a zirconium oxide material, a perovskite structure material, and a noble metal material formed between the zirconium oxide material and the perovskite structure material.Type: GrantFiled: August 31, 2012Date of Patent: January 28, 2014Assignee: Micron Technology, Inc.Inventors: Dale W. Collins, D. V. Nirmal Ramaswamy, Matthew N. Rocklein, Swapnil A. Lengade
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Patent number: 8603318Abstract: An electrolyte solution, methods, and systems for selectively removing a conductive metal from a substrate are provided. The electrolyte solution comprising nanoparticles that are more noble than the conductive metal being removed, is applied to a substrate to remove the conductive metal selectively relative to a dielectric material without application of an external potential or contact of a processing pad with a surface of the substrate. The solutions and methods can be applied, for example, to remove a conductive metal layer (e.g., barrier metal) selectively relative to a dielectric material and to a materially different conductive metal (e.g., copper interconnect) without application of an external potential or contact of a processing pad with the surface of the substrate.Type: GrantFiled: May 2, 2011Date of Patent: December 10, 2013Assignee: Micron Technology, Inc.Inventors: Rita J. Klein, Dale W. Collins, Paul Morgan, Joseph N. Greeley, Nishant Sinha
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Publication number: 20130193394Abstract: Electronic apparatus, systems, and methods include a resistive random access memory cell having an oxygen gradient in a variable resistive region of the resistive random access memory cell and methods of forming the resistive random access memory cell. Oxygen can be incorporated into the resistive random access memory cell by ion implantation. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: January 30, 2012Publication date: August 1, 2013Inventors: Swapnil Lengade, Dale W. Collins, Durai Vishak Nirmal Ramaswamy, Yongjun Jeff Hu
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Publication number: 20130175494Abstract: Memory cells (e.g., CBRAM cells) include an ion source material over an active material and an electrode comprising metal silicide over the ion source material. The ion source material may include at least one of a chalcogenide material and a metal. Apparatuses, such as systems and devices, include a plurality of such memory cells. Memory cells include an adhesion material of metal silicide between a ion source material and an electrode of elemental metal. Methods of forming a memory cell include forming a first electrode, forming an active material, forming an ion source material, and forming a second electrode including metal silicide over the metal ion source material. Methods of adhering a material including copper and a material including tungsten include forming a tungsten silicide material over a material including copper and treating the materials.Type: ApplicationFiled: January 11, 2012Publication date: July 11, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Dale W. Collins, Marko Milojevic, Scott E. Sills, Si-Young Park
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Publication number: 20130109147Abstract: Some embodiments include methods of forming memory cells. Metal oxide may be deposited over a first electrode, with the deposited metal oxide having a relatively low degree of crystallinity. The degree of crystallinity within the metal oxide may be increased after the deposition of the metal oxide. A dielectric material may be formed over the metal oxide, and a second electrode may be formed over the dielectric material. The degree of crystallinity may be increased with a thermal treatment. The thermal treatment may be conducted before, during, and/or after formation of the dielectric material.Type: ApplicationFiled: October 26, 2011Publication date: May 2, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Noel Rocklein, D.V. Nirmal Ramaswamy, Dale W. Collins, Swapnil Lengade, Srividya Krishnamurthy, Mark Korber
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Publication number: 20120315754Abstract: Interconnects containing ruthenium and methods of forming can include utilization of a sacrificial protective material. Planarization or other material removal operations can be performed on a substrate having a recess, the recess containing a ruthenium containing material along with the sacrificial protective material. The protective material is later removed, and a conductor can be filled in the remaining recess.Type: ApplicationFiled: June 8, 2011Publication date: December 13, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Xiaoyun Zhu, Dale W. Collins, Joseph Lindgren, Anurag Jindal
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Publication number: 20120043658Abstract: Some embodiments include methods for depositing copper-containing material utilizing physical vapor deposition of the copper-containing material while keeping a temperature of the deposited copper-containing material at greater than 100° C. Some embodiments include methods in which openings are lined with a metal-containing composition, copper-containing material is physical vapor deposited over the metal-containing composition while a temperature of the copper-containing material is no greater than about 0° C., and the copper-containing material is then annealed while the copper-containing material is at a temperature in a range of from about 180° C. to about 250° C. Some embodiments include methods in which openings are lined with a composition containing metal and nitrogen, and the lined openings are at least partially filled with copper-containing material.Type: ApplicationFiled: August 20, 2010Publication date: February 23, 2012Inventors: Dale W. Collins, Joe Lindgren
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Publication number: 20110203940Abstract: An electrolyte solution, methods, and systems for selectively removing a conductive metal from a substrate are provided. The electrolyte solution comprising nanoparticles that are more noble than the conductive metal being removed, is applied to a substrate to remove the conductive metal selectively relative to a dielectric material without application of an external potential or contact of a processing pad with the surface of the substrate. The solutions and methods can be applied, for example, to remove a conductive metal layer (e.g., barrier metal) selectively relative to dielectric material and to a materially different conductive metal (e.g., copper interconnect) without application of an external potential or contact of a processing pad with the surface of the substrate.Type: ApplicationFiled: May 2, 2011Publication date: August 25, 2011Inventors: Rita J. Klein, Dale W. Collins, Paul Morgan, Joseph N. Greeley, Nishant Sinha
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Patent number: 7935242Abstract: An electrolyte solution, methods, and systems for selectively removing a conductive metal from a substrate are provided. The electrolyte solution comprising nanoparticles that are more noble than the conductive metal being removed, is applied to a substrate to remove the conductive metal selectively relative to a dielectric material without application of an external potential or contact of a processing pad with the surface of the substrate. The solutions and methods can be applied, for example, to remove a conductive metal layer (e.g., barrier metal) selectively relative to dielectric material and to a materially different conductive metal (e.g., copper interconnect) without application of an external potential or contact of a processing pad with the surface of the substrate.Type: GrantFiled: August 21, 2006Date of Patent: May 3, 2011Assignee: Micron Technology, Inc.Inventors: Rita J. Klein, Dale W. Collins, Paul Morgan, Joseph N. Greeley, Nishant Sinha
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Patent number: 7700478Abstract: The present teachings and illustrations describe a process for forming a plurality of conductive structures in or on a substrate. In one embodiment, the process comprises forming a plurality of recesses in or on the substrate, wherein the plurality of recesses include recesses having different dimensions. In addition, the process further comprises (i) forming a conductive layer which at least partially fills the plurality of recesses and (ii) treating the conductive layer to improve the conductive properties of the conductive layer. Moreover, the process still further comprises (iii) sequentially repeating acts (i) and (ii) until each of the recesses of the plurality of recesses are filled to a desired dimension and such that the conductive material in the recesses of smaller dimension are more uniformly adhered to the bottom surfaces of the recesses.Type: GrantFiled: March 6, 2007Date of Patent: April 20, 2010Assignee: Micron Technology, Inc.Inventor: Dale W. Collins
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Patent number: 7666776Abstract: The invention includes methods of forming pluralities of electrically conductive structures. The methods can include formation of a gradient-containing material across a substrate and in direct physical contact with conductive surfaces of nodes. The gradient-containing material can consist essentially of tantalum nitride at a lowermost portion in contact with the conductive surfaces, consist essentially of tantalum at an uppermost portion, and have a TaN/Ta gradient extending between the lowermost and uppermost portions. Alternatively, the gradient-containing material can have a Co/W gradient extending therethrough. Conductive structures can be formed over the gradient-containing material. The invention also includes constructions comprising electrically conductive lines over a material having a TaN/Ta gradient, or a W/Co gradient, extending therethrough.Type: GrantFiled: September 1, 2005Date of Patent: February 23, 2010Assignee: Micron Technology, Inc.Inventors: Dale W. Collins, Rita J. Klein, James E. Green
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Patent number: 7498670Abstract: Methods are provided for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are deposited on the wall of the via, reacting with the surface of the wall until the entire wall is covered by the lining material. The lining material is then fixed in place to form a layer lining the via. The lined via may then be filled with a desired material. For example, a via lined with an insulative material may be filled with a material such as copper to create an insulated conductive via through the substrate.Type: GrantFiled: August 15, 2006Date of Patent: March 3, 2009Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, Dale W. Collins, Steven M. McDonald
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Patent number: 7446415Abstract: Methods of electroless filling electrically different features such as contact openings to form interconnects and conductive contacts, and semiconductor devices, dies, and systems that incorporate the interconnects and contacts are disclosed. The contact openings are electrically shorted together with a selective material, a nucleation layer is selectively deposited onto the area to be plated (e.g., the base of the opening), and a conductive material is electroless plated onto the nucleation layer to fill the opening. The process achieves substantially simultaneous filling of openings having different surface potentials at an about even rate.Type: GrantFiled: March 9, 2005Date of Patent: November 4, 2008Assignee: Micron Technology, Inc.Inventors: Dale W Collins, Rita J Klein
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Patent number: 7405007Abstract: A method of electroplating metal onto a low conductivity layer combines a potential or current reversal waveform with variation in the amplitude and duration of the applied potential or current pulse. The method includes, over time, varying the duration of the pulse and continuously decreasing the amplitude of both the cathodic and anodic portions of the waveform across the surface of the low conductivity layer as the deposition zone moves from the center of the surface of the low conductivity layer to the outside edge. By virtue of the ability to vary the amplitude and duration of the pulse, the method facilitates the filling of structures in the center of the low conductivity layer without overdepositing on the outside edge, thus ensuring a controlled deposition of material across the surface of the low conductivity layer.Type: GrantFiled: March 26, 2003Date of Patent: July 29, 2008Assignee: Micron Technology, Inc.Inventor: Dale W. Collins