Patents by Inventor Daniel C. Edelstein

Daniel C. Edelstein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ULTRATHIN SUPERLATTICE OF MnO/Mn/MnN AND OTHER METAL OXIDE/METAL/METAL NITRIDE LINERS AND CAPS FOR COPPER LOW DIELECTRIC CONSTANT INTERCONNECTS
    Publication number: 20160133576
    Abstract: An electrical device comprising including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure. The liner includes a superlattice structure comprised of a metal oxide layer, a metal layer present on the metal oxide layer, and a metal nitride layer that is present on the metal layer. A first layer of the superlattice structure that is in direct contact with the low-k dielectric material is one of said metal oxide layer and a final layer of the superlattice structure that is in direct contact with the copper including structure is one of the metal nitride layers.
    Type: Application
    Filed: December 28, 2015
    Publication date: May 12, 2016
    Inventors: Donald F. Canaperi, Daniel C. Edelstein, Alfred Grill, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga Shobha
  • Microelectronic structure including air gap
    Patent number: 9332628
    Abstract: A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: May 3, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Daniel C. Edelstein, David V. Horak, Elbert E. Huang, Satyanarayana V. Nitta, Takeshi Nogami, Shom Ponoth, Terry A. Spooner
  • Interconnect structures with fully aligned vias
    Patent number: 9324650
    Abstract: A method of forming a fully aligned via connecting two metal lines on different Mx levels by forming a recessed opening above a first metal line in a first ILD; forming a cap on the first ILD and in the recessed openings; forming a second ILD on the cap; forming a metal trench hardmask above the second ILD, forming a metal trench pattern in the metal trench hardmask; forming a via pattern that is self aligned to the metal trench pattern and above a portion of the first metal line; forming a via opening exposing the first metal line by transferring the via pattern and metal trench pattern to lower levels, the via pattern is self-aligned to the recessed opening; and forming a via and a third metal line in the via opening and the transferred metal trench pattern, respectively.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: April 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Nicholas C. Fuller, Elbert E. Huang, Satyanarayana V. Nitta, David L. Rath
  • Beol structures incorporating active devices and mechanical strength
    Patent number: 9318415
    Abstract: An integrated circuit and method includes a substrate, a plurality of semiconductor device layers monolithically integrated on the substrate, and a metal wiring layer with vias interconnecting the plurality of semiconductor device layers. The semiconductor device layers are devoid of bonding or joining interface with the substrate.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: April 19, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Stephen M Gates, Daniel C. Edelstein, Satyanarayana V. Nitta
  • Altering capacitance of MIM capacitor having reactive layer therein
    Patent number: 9299765
    Abstract: Embodiments include a metal-insulator-metal (MIM) capacitor having: a first electrode; a second electrode disposed proximate the first electrode; an insulator layer between the first and second electrodes; and a reactive layer positioned proximate the insulator layer and configured to allow altering of the reactive layer to change a capacitive value of the MIM capacitor, the reactive layer including a reactive conductor.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: March 29, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Daniel C. Edelstein, Anthony K. Stamper
  • SINGLE DAMASCENE INTERCONNECT STRUCTURE
    Publication number: 20160071802
    Abstract: A single damascene interconnect structure which includes a first layer that includes a first dielectric material having a first filled opening that has a barrier layer of a refractory material with Cu filling the first filled opening. Also included is a second layer of a second dielectric material having a second filled opening that has a sidewall layer which includes a compound of a metal, O, and Si such that the metal is Mn, Ti and Al, and with Cu filling the second filled opening. The compound is in direct contact with the second dielectric material. The first layer is adjacent to the second layer and the first filled opening is aligned with the second filled opening so that the first filled opening is a via and the second filled opening is a trench.
    Type: Application
    Filed: October 20, 2015
    Publication date: March 10, 2016
    Inventors: Shyng-Tsong Chen, Daniel C. Edelstein, Takeshi Nogami
  • BEOL structures incorporating active devices and mechanical strength
    Patent number: 9275936
    Abstract: A method of fabricating a monolithic integrated circuit using a single substrate, the method including forming a first semiconductor layer from a substrate, fabricating semiconductor devices on the substrate, fabricating at least one metal wiring layer on the semiconductor devices, forming at least one dielectric layer in integral contact with the at least one metal wiring layer, forming contact openings through the at least one dielectric layer to expose regions of the at least one metal wiring layer, integrally forming, from the substrate, a second semiconductor layer on the dielectric layer, and in contact with the at least one metal wiring layer through the contact openings, and forming a plurality of non-linear semiconductor devices in said second semiconductor layer.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: March 1, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Stephen M. Gates, Daniel C. Edelstein, Satyanarayana V. Nitta
  • Ultrathin superlattice of MnO/Mn/MnN and other metal oxide/metal/metal nitride liners and caps for copper low dielectric constant interconnects
    Patent number: 9275952
    Abstract: An electrical device including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure. The liner includes a superlattice structure comprised of a metal oxide layer, a metal layer present on the metal oxide layer, and a metal nitride layer that is present on the metal layer. A first layer of the superlattice structure that is in direct contact with the low-k dielectric material is one of said metal oxide layer and a final layer of the superlattice structure that is in direct contact with the copper including structure is one of the metal nitride layers.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: March 1, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Donald F. Canaperi, Daniel C. Edelstein, Alfred Grill, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga Shobha
  • STRUCTURE WITH SELF ALIGNED RESIST LAYER ON AN INTERCONNECT SURFACE AND METHOD OF MAKING SAME
    Publication number: 20160056106
    Abstract: A structure is provided with a self-aligned resist layer on a surface of metal interconnects for use in forming air gaps in an insulator material and method of fabricating the same. The non-lithographic method includes applying a resist on a structure comprising at least one metal interconnect formed in an insulator material. The method further includes blanket-exposing the resist to energy and developing the resist to expose surfaces of the insulator material while protecting the metal interconnects. The method further includes forming air gaps in the insulator material by an etching process, while the metal interconnects remain protected by the resist.
    Type: Application
    Filed: November 4, 2015
    Publication date: February 25, 2016
    Inventors: Daniel C. EDELSTEIN, Elbert E. HUANG, Robert D. MILLER
  • INTERCONNECT STRUCTURE
    Publication number: 20160056112
    Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.
    Type: Application
    Filed: October 14, 2015
    Publication date: February 25, 2016
    Inventors: Daniel C. EDELSTEIN, Son V. NGUYEN, Takeshi NOGAMI, Deepika PRIYADARSHINI, Hosadurga K. SHOBHA
  • INTERCONNECT STRUCTURE
    Publication number: 20160056076
    Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.
    Type: Application
    Filed: August 22, 2014
    Publication date: February 25, 2016
    Inventors: Daniel C. EDELSTEIN, Son V. NGUYEN, Takeshi NOGAMI, Deepika PRIYADARSHINI, Hosadurga K. SHOBHA
  • INTERCONNECT STRUCTURES WITH FULLY ALIGNED VIAS
    Publication number: 20160049364
    Abstract: A method of forming a fully aligned via connecting two metal lines on different Mx levels by forming a recessed opening above a first metal line in a first ILD; forming a cap on the first ILD and in the recessed openings; forming a second ILD on the cap; forming a metal trench hardmask above the second ILD, forming a metal trench pattern in the metal trench hardmask; forming a via pattern that is self aligned to the metal trench pattern and above a portion of the first metal line; forming a via opening exposing the first metal line by transferring the via pattern and metal trench pattern to lower levels, the via pattern is self-aligned to the recessed opening; and forming a via and a third metal line in the via opening and the transferred metal trench pattern, respectively.
    Type: Application
    Filed: August 15, 2014
    Publication date: February 18, 2016
    Inventors: Daniel C. Edelstein, Nicholas C. Fuller, Elbert E. Huang, Satyanarayana V. Nitta, David L. Rath
  • ULTRATHIN SUPERLATTICE OF MnO/Mn/MnN AND OTHER METAL OXIDE/METAL/METAL NITRIDE LINERS AND CAPS FOR COPPER LOW DIELECTRIC CONSTANT INTERCONNECTS
    Publication number: 20160035618
    Abstract: An electrical device including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure. The liner includes a superlattice structure comprised of a metal oxide layer, a metal layer present on the metal oxide layer, and a metal nitride layer that is present on the metal layer. A first layer of the superlattice structure that is in direct contact with the low-k dielectric material is one of said metal oxide layer and a final layer of the superlattice structure that is in direct contact with the copper including structure is one of the metal nitride layers.
    Type: Application
    Filed: October 15, 2015
    Publication date: February 4, 2016
    Inventors: Donald F. Canaperi, Daniel C. Edelstein, Alfred Grill, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga Shobha
  • Formation of alloy liner by reaction of diffusion barrier and seed layer for interconnect application
    Patent number: 9245794
    Abstract: An interconnect structure including an alloy liner positioned directly between a diffusion barrier and a Cu alloy seed layer as well as methods for forming such an interconnect structure are provided. The alloy liner of the present invention is formed by thermally reacting a previously deposited diffusion barrier metal alloy layer with an overlying Cu alloy seed layer. During the thermal reaction, the metal alloys from the both the diffusion barrier and the Cu alloys seed layer react forming a metal alloy reaction product between the diffusion barrier and the Cu seed layer.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: January 26, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chih-Chao Yang, Daniel C. Edelstein, Takeshi Nogami
  • Single damascene interconnect structure
    Patent number: 9224686
    Abstract: A single damascene interconnect structure which includes a first layer of a first dielectric material having a first filled opening that has a sidewall layer which includes a compound of a metal, O, and Si such that the metal is Mn, Ti and Al, and with Cu filling the first filled opening. The compound is in direct contact with the first dielectric material. Also included is a second layer that includes a second dielectric material having a second filled opening that has a barrier layer of a refractory material with Cu filling the second filled opening. The first layer is adjacent to the second layer and the first filled opening is aligned with the second filled opening so that one of the first and second filled openings is a via and the other of the first and second filled openings is a trench.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: December 29, 2015
    Assignee: International Business Machines Corporation
    Inventors: Shyng-Tsong Chen, Daniel C. Edelstein, Takeshi Nogami
  • Structure with self aligned resist layer on an interconnect surface and method of making same
    Patent number: 9202863
    Abstract: A structure is provided with a self-aligned resist layer on a surface of metal interconnects for use in forming air gaps in an insulator material and method of fabricating the same. The non-lithographic method includes applying a resist on a structure which has at least one metal interconnect formed in an insulator material. The method further includes blanket-exposing the resist to energy and developing the resist to expose surfaces of the insulator material while protecting the metal interconnects. The method further includes forming air gaps in the insulator material by an etching process, while the metal interconnects remain protected by the resist.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: December 1, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Daniel C. Edelstein, Elbert E. Huang, Robert D. Miller
  • SELF-FORMING EMBEDDED DIFFUSION BARRIERS
    Publication number: 20150340323
    Abstract: Interconnect structures containing metal oxide embedded diffusion barriers and methods of forming the same. Interconnect structures may include an Mx level including an Mx metal in an Mx dielectric, an Mx+1 level above the Mx level including an Mx+1 metal in an Mx+1 dielectric, an embedded diffusion barrier adjacent to the Mx+1 dielectric; and a seed alloy region adjacent to the Mx+1 metal separating the Mx metal from the Mx+1 metal. The embedded diffusion barrier may include a barrier-forming material such as manganese, aluminum, titanium, or some combination thereof. The seed alloy region may include a seed material such as cobalt, ruthenium, or some combination thereof.
    Type: Application
    Filed: August 4, 2015
    Publication date: November 26, 2015
    Inventors: Cyril Cabral, JR., Daniel C. Edelstein, Juntao Li, Takeshi Nogami
  • Self-forming embedded diffusion barriers
    Patent number: 9190321
    Abstract: Interconnect structures containing metal oxide embedded diffusion barriers and methods of forming the same. Interconnect structures may include an Mx level including an Mx metal in an Mx dielectric, an Mx+1 level above the Mx level including an Mx+1 metal in an Mx+1 dielectric, an embedded diffusion barrier adjacent to the Mx+1 dielectric; and a seed alloy region adjacent to the Mx+1 metal separating the Mx metal from the Mx+1 metal. The embedded diffusion barrier may include a barrier-forming material such as manganese, aluminum, titanium, or some combination thereof. The seed alloy region may include a seed material such as cobalt, ruthenium, or some combination thereof.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: November 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Daniel C. Edelstein, Juntao Li, Takeshi Nogami
  • Alignment of integrated circuit chip stack
    Patent number: 9171742
    Abstract: The present disclosure relates to methods and devices for manufacturing a three-dimensional chip package. A method includes forming a linear groove on an alignment rail, attaching an alignment rod to the linear groove, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail. Another method includes forming an alignment ridge on an alignment rail, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: October 27, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Evan G. Colgan, Steven A. Cordes, Daniel C. Edelstein, Vijayeshwar D. Khanna, Kenneth Latzko, Qinghuang Lin, Peter J. Sorce, Sri M. Sri-Jayantha, Robert L. Wisnieff, Roy R. Yu
  • MICROELECTRONIC STRUCTURE INCLUDING AIR GAP
    Publication number: 20150289361
    Abstract: A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.
    Type: Application
    Filed: June 15, 2015
    Publication date: October 8, 2015
    Inventors: Daniel C. Edelstein, David V. Horak, Elbert E. Huang, Satyanarayana V. Nitta, Takeshi Nogami, Shom Ponoth, Terry A. Spooner