Abstract: An electrical contact structure for an integrated circuit device is described. A first patterned dielectric layer comprising at least one contact hole, the contact hole including a bottom surface, and sidewalls extending from the bottom surface to a top surface is provided. A tungsten via is disposed within the at least one contact hole, the tungsten via having a bottom surface in contact with a lower layer of the device and a top surface. A selectively deposited metal layer is disposed on the top surface of the tungsten via to repair etch damage.

Abstract: In one aspect of the invention, a method for fabricating an advanced metal conductor structure includes a conductive line pattern including a set of conductive line trenches in a dielectric layer. Each conductive line trench of the conductive line pattern has parallel vertical sidewalls and a horizontal bottom. A surface treatment of the dielectric layer is performed. The surface treatment produces an element enriched surface layer in which a concentration of a selected element in a surface portion of the parallel sidewalls and horizontal bottoms of the conductive line trenches is increased. A first metal layer is deposited on the element enriched surface layer. A first thermal anneal is performed which simultaneously reflows the first metal layer to fill a first portion of the conductive line trenches and causes a chemical change at interfaces of the first metal layer and the element enriched surface layer creating a liner which is an alloy of the first metal and selected element.

Abstract: Recrystallization and grain growth of an interconnect metal, such as Cu, is achieved at higher anneal temperatures of 150° C. to 600° C., for example, for short anneal times of five to 180 minutes by forming a metal stress locking layer on the interconnect metal before anneal and chemical-mechanical polishing. The stress locking layer extends the elastic region of the interconnect metal by suppressing atom diffusion to the free surface, resulting in near zero tensile stress at room temperature after anneal. Stress voiding, which creates reliability problems, is thereby avoided. Improved grain size and texture are also achieved. The stress locking layer is removed after anneal by chemical-mechanical polishing or wet etching leaving the metal interconnect with low stress and improved grain size and texture. Annealing can be done in a forming gas or nitrogen gas atmosphere.

Abstract: In one aspect of the invention, a method for fabricating an advanced metal conductor structure includes providing a conductive line pattern including a set of conductive line trenches in a dielectric layer. Each conductive line trench of the conductive line pattern having parallel vertical sidewalls and a horizontal bottom. A surface treatment of the dielectric layer is performed. The surface treatment produces an element enriched surface layer in which a concentration of a selected element in a surface portion of the parallel sidewalls and horizontal bottoms of the conductive line trenches is increased. A first metal layer is deposited on the element enriched surface layer. A first thermal anneal is performed which simultaneously reflows the first metal layer to fill a first portion of the conductive line trenches and causes a chemical change at interfaces of the first metal layer and the element enriched surface layer creating a liner which is an alloy of the first metal and selected element.

Abstract: A pattern is provided in a dielectric layer in which a set of features are patterned for a set of metal conductor structures. An adhesion promoting layer is created disposed over the patterned dielectric. A metal layer is deposited to fill a first portion of the set of features disposed the adhesion promoting layer. A ruthenium layer is deposited disposed over the metal layer. Using a physical vapor deposition process, a cobalt layer is deposited disposed over the ruthenium layer. A thermal anneal reflows the cobalt layer to fill a second portion of the set of features. In another aspect of the invention, a device created by the method is described.

Abstract: A first semiconductor structure including a first bonding oxide layer having a first metallic structure embedded therein and a second semiconductor structure including a second bonding oxide layer having second metallic structure embedded therein are provided. A high-k dielectric material is formed on a surface of the first metallic structure. A nitride surface treatment process is performed to provide a nitrided surface layer to each structure. The nitrided surface layer includes nitridized oxide regions located in an upper portion of the bonding oxide layers and either a nitridized high-k dielectric material located in at least an upper portion of the high k dielectric material or a nitridized metallic region located in an upper portion of the second metallic structure. The nitrogen within the nitridized metallic region is then selectively removed to restore the upper portion of the second metallic structure to its original composition. Bonding is then performed.

Abstract: A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.

Abstract: Interconnect structures containing metal oxide embedded diffusion barriers and methods of forming the same. Interconnect structures may include an Mx level including an Mx metal in an Mx dielectric, an Mx+1 level above the Mx level including an Mx+1 metal in an Mx+1 dielectric, an embedded diffusion barrier adjacent to the Mx+1 dielectric; and a seed alloy region adjacent to the Mx+1 metal separating the Mx metal from the Mx+1 metal. The embedded diffusion barrier may include a barrier-forming material such as manganese, aluminum, titanium, or some combination thereof. The seed alloy region may include a seed material such as cobalt, ruthenium, or some combination thereof.

Abstract: An electrical device including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure. The liner includes a superlattice structure comprised of a metal oxide layer, a metal layer present on the metal oxide layer, and a metal nitride layer that is present on the metal layer. A first layer of the superlattice structure that is in direct contact with the low-k dielectric material is one of said metal oxide layer and a final layer of the superlattice structure that is in direct contact with the copper including structure is one of the metal nitride layers.

Abstract: A structure comprising a first dielectric layer embedded with a first interconnect structure; an insulator layer disposed on the first dielectric layer; a second dielectric layer disposed on the insulator layer; a via residing within the second dielectric layer; and a second interconnect structure isolated from the first dielectric layer. Further, a diffusion barrier layer is configured to isolate the first interconnect structure from the first dielectric layer and the insulator layer. Further, a first portion of a bottom surface of the via resides on a top surface of the insulator layer, a second portion of the bottom surface of the via resides on a first portion of a top surface of the first interconnect structure. Moreover, a capping layer residing on a second portion of the top surface of the first interconnect structure and a first portion of a bottom surface of the second dielectric layer.

Abstract: A semiconductor structure comprising a first semiconductor structure; a second semiconductor structure; and a silicon-nitride layer configured to bond the first semiconductor structure and second semiconductor structure together. The first semiconductor structure comprises a first wafer; a first dielectric layer; a first interconnect structure; and a first oxide layer. The second semiconductor structure comprises a second wafer; a second dielectric layer; a second interconnect structure; and a second oxide layer. The structure further comprises a first nitride layer residing on a top surface of the first oxide layer formed by a nitridation process of the top surface of the first oxide layer; and a second nitride layer residing on a top surface of the second oxide layer formed by the nitridation process of the top surface of the second oxide layer. Further, the silicon-nitride layer comprises the first nitride layer and the second nitride layer.

Abstract: Recrystallization and grain growth of an interconnect metal, such as Cu, is achieved at higher anneal temperatures of 150° C. to 600° C., for example, for short anneal times of five to 180 minutes by forming a metal stress locking layer on the interconnect metal before anneal and chemical-mechanical polishing. The stress locking layer extends the elastic region of the interconnect metal by suppressing atom diffusion to the free surface, resulting in near zero tensile stress at room temperature after anneal. Stress voiding, which creates reliability problems, is thereby avoided. Improved grain size and texture are also achieved. The stress locking layer is removed after anneal by chemical-mechanical polishing or wet etching leaving the metal interconnect with low stress and improved grain size and texture. Annealing can be done in a forming gas or nitrogen gas atmosphere.

Abstract: A bipolar junction transistor comprises a semiconductor layer disposed on an insulating material, at least a portion of the semiconductor layer forming a base region. The bipolar junction transistor further comprises a transistor emitter laterally disposed on a first side of the base region, where in the transistor emitter is a first doping type and has a first width, and wherein the first width is a lithographic feature size. The bipolar junction transistor further comprises a transistor collector laterally disposed on a second side of the base region, wherein the transistor collector is the first doping type and the first width. The bipolar junction transistor further comprises a central base contact laterally disposed on the base region between the transistor emitter and the transistor collector, wherein the central base contact is a second doping type and has a second width, and wherein the second width is a sub-lithographic feature size.

Abstract: An electrical contact structure for an integrated circuit device is described. A first patterned dielectric layer comprising at least one contact hole, the contact hole including a bottom surface, and sidewalls extending from the bottom surface to a top surface is provided. The bottom surface of the dielectric layer is in contact with a lower layer of the integrated circuit device. A tungsten via is disposed within the at least one contact hole, the tungsten via having a bottom surface in contact with the lower layer and a top surface. A tungsten nitride layer is disposed on the top surface of the tungsten via to repair etch damage done to the tungsten via.

Abstract: Structures and processes include a single metallization step for forming a metal nitride liner layer suitable for contact formation. The structure and processes generally includes forming a nitrogen-enriched surface in a deposited metal liner layer or forming a nitrogen-enriched surface in the dielectric material prior to deposition of the metal liner layer. In this manner, nitridization of the metal occurs upon deposition of nitrogen ions into the metal liner layer and/or as a function of additional conventional processing in fabricating the integrated circuit such that the deposited nitrogen ions diffuse into at least a portion of the metal liner layer. As a consequence, only a single metal layer deposition step is needed to form the metal liner layer.

Abstract: Structures and processes include a single metallization step for forming a metal nitride liner layer suitable for contact formation. The structure and processes generally includes forming a nitrogen-enriched surface in a deposited metal liner layer or forming a nitrogen-enriched surface in the dielectric material prior to deposition of the metal liner layer. In this manner, nitridization of the metal occurs upon deposition of nitrogen ions into the metal liner layer and/or as a function of additional conventional processing in fabricating the integrated circuit such that the deposited nitrogen ions diffuse into at least a portion of the metal liner layer. As a consequence, only a single metal layer deposition step is needed to form the metal liner layer.

Abstract: An electrical contact structure for an integrated circuit device is described. A first patterned dielectric layer comprising at least one contact hole, the contact hole including a bottom surface, and sidewalls extending from the bottom surface to a top surface is provided. The bottom surface of the dielectric layer is in contact with a lower layer of the integrated circuit device. A tungsten via is disposed within the at least one contact hole, the tungsten via having a bottom surface in contact with the lower layer and a top surface. A tungsten nitride layer is disposed on the top surface of the tungsten via to repair etch damage done to the tungsten via.

Abstract: An electrical contact structure for an integrated circuit device is described. A first patterned dielectric layer comprising at least one contact hole, the contact hole including a bottom surface, and sidewalls extending from the bottom surface to a top surface is provided. A tungsten via is disposed within the at least one contact hole, the tungsten via having a bottom surface in contact with a lower layer of the device and a top surface. A selectively deposited metal layer is disposed on the top surface of the tungsten via to repair etch damage.

Abstract: A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.

Abstract: Structures and processes include a single metallization step for forming a metal nitride liner layer suitable for contact formation. The structure and processes generally includes forming a nitrogen-enriched surface in a deposited metal liner layer or forming a nitrogen-enriched surface in the dielectric material prior to deposition of the metal liner layer. In this manner, nitridization of the metal occurs upon deposition of nitrogen ions into the metal liner layer and/or as a function of additional conventional processing in fabricating the integrated circuit such that the deposited nitrogen ions diffuse into at least a portion of the metal liner layer. As a consequence, only a single metal layer deposition step is needed to form the metal liner layer.