Patents by Inventor Daniel C. Edelstein
Daniel C. Edelstein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170140981Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.Type: ApplicationFiled: January 27, 2017Publication date: May 18, 2017Inventors: Daniel C. EDELSTEIN, Son V. NGUYEN, Takeshi NOGAMI, Deepika PRIYADARSHINI, Hosadurga K. SHOBHA
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Patent number: 9653403Abstract: Structures and processes include a single metallization step for forming a metal nitride liner layer suitable for contact formation. The structure and processes generally includes forming a nitrogen-enriched surface in a deposited metal liner layer or forming a nitrogen-enriched surface in the dielectric material prior to deposition of the metal liner layer. In this manner, nitridization of the metal occurs upon deposition of nitrogen ions into the metal liner layer and/or as a function of additional conventional processing in fabricating the integrated circuit such that the deposited nitrogen ions diffuse into at least a portion of the metal liner layer. As a consequence, only a single metal layer deposition step is needed to form the metal liner layer.Type: GrantFiled: April 21, 2016Date of Patent: May 16, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel C. Edelstein, Baozhen Li, Chih-Chao Yang
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Patent number: 9653567Abstract: A bipolar junction transistor comprises a semiconductor layer disposed on an insulating material, at least a portion of the semiconductor layer forming a base region. The bipolar junction transistor further comprises a transistor emitter laterally disposed on a first side of the base region, where in the transistor emitter is a first doping type and has a first width, and wherein the first width is a lithographic feature size. The bipolar junction transistor further comprises a transistor collector laterally disposed on a second side of the base region, wherein the transistor collector is the first doping type and the first width. The bipolar junction transistor further comprises a central base contact laterally disposed on the base region between the transistor emitter and the transistor collector, wherein the central base contact is a second doping type and has a second width, and wherein the second width is a sub-lithographic feature size.Type: GrantFiled: July 18, 2016Date of Patent: May 16, 2017Assignee: International Business Machines CorporationInventors: Fabio Carta, Daniel C. Edelstein, Stephen M. Gates, Bahman Hekmatshoartabari, Tak H. Ning
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Patent number: 9646931Abstract: In one aspect of the invention, a method for fabricating an advanced metal conductor structure includes a conductive line pattern including a set of conductive line trenches in a dielectric layer. Each conductive line trench of the conductive line pattern has parallel vertical sidewalls and a horizontal bottom. A surface treatment of the dielectric layer is performed. The surface treatment produces an element enriched surface layer in which a concentration of a selected element in a surface portion of the parallel sidewalls and horizontal bottoms of the conductive line trenches is increased. A first metal layer of a first metal having a first conductivity is deposited on the element enriched surface layer.Type: GrantFiled: July 22, 2016Date of Patent: May 9, 2017Assignee: International Business Machines CorporationInventors: Daniel C Edelstein, Chih-Chao Yang
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Patent number: 9620481Abstract: A metallic dopant element having a greater oxygen-affinity than copper is introduced into, and/or over, surface portions of copper-based metal pads and/or surfaces of a dielectric material layer embedding the copper-based metal pads in each of two substrates to be subsequently bonded. A dopant-metal silicate layer may be formed at the interface between the two substrates to contact portions of metal pads not in contact with a surface of another metal pad, thereby functioning as an oxygen barrier layer, and optionally as an adhesion material layer. A dopant metal rich portion may be formed in peripheral portions of the metal pads in contact with the dopant-metal silicate layer. A dopant-metal oxide portion may be formed in peripheral portions of the metal pads that are not in contact with a dopant-metal silicate layer.Type: GrantFiled: May 19, 2015Date of Patent: April 11, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Daniel C. Edelstein, Douglas C. La Tulipe, Jr., Wei Lin, Deepika Priyadarshini, Spyridon Skordas, Tuan A. Vo, Kevin R. Winstel
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Patent number: 9620479Abstract: A first semiconductor structure including a first bonding oxide layer having a metal resistor structure embedded therein and a second semiconductor structure including a second bonding oxide layer having a metallic bonding structure embedded therein are provided. A nitride surface treatment process is performed to provide a nitrided surface layer to each structure. Each nitrided surface layer includes nitridized oxide regions located in an upper portion of the bonding oxide layer and nitridized metallic regions located in an upper portion of either the metal resistor structure or the metallic bonding structure. The nitrogen within the nitridized metallic region located in the upper portion of the metallic bonding structure is then selectively removed to restore the upper portion of the metallic bonding structure to its original composition. Bonding is then performed to form a dielectric bonding interface and a metallic bonding interface between.Type: GrantFiled: June 30, 2016Date of Patent: April 11, 2017Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Chih-Chao Yang
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Patent number: 9601432Abstract: An electrical contact structure for an integrated circuit device is described. A first patterned dielectric layer comprising at least one contact hole, the contact hole including a bottom surface, and sidewalls extending from the bottom surface to a top surface is provided. A tungsten via is disposed within the at least one contact hole, the tungsten via having a bottom surface in contact with a lower layer of the device and a top surface. A selectively deposited metal layer is disposed on the top surface of the tungsten via to repair etch damage.Type: GrantFiled: November 23, 2015Date of Patent: March 21, 2017Assignee: International Business Machines CorporationInventors: Daniel C Edelstein, Chih-Chao Yang
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Patent number: 9601371Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.Type: GrantFiled: October 14, 2015Date of Patent: March 21, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel C. Edelstein, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga K. Shobha
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Patent number: 9583410Abstract: A volumetric integrated circuit manufacturing method is provided. The method includes assembling a slab element of elongate chips, exposing a wiring layer between adjacent elongate chips of the slab element, metallizing a surface of the slab element at and around the exposed wiring layer to form a metallized surface electrically coupled to the wiring layer and passivating the metallized surface to hermetically seal the metallized surface.Type: GrantFiled: March 21, 2014Date of Patent: February 28, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel C. Edelstein, Michael A. Gaynes, Thomas M. Shaw, Bucknell C. Webb, Roy R. Yu
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Publication number: 20170005040Abstract: An electrical device including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure. The liner includes a superlattice structure comprised of a metal oxide layer, a metal layer present on the metal oxide layer, and a metal nitride layer that is present on the metal layer. A first layer of the superlattice structure that is in direct contact with the low-k dielectric material is one of said metal oxide layer and a final layer of the superlattice structure that is in direct contact with the copper including structure is one of the metal nitride layers.Type: ApplicationFiled: September 16, 2016Publication date: January 5, 2017Inventors: Donald F. Canaperi, Daniel C. Edelstein, Alfred Grill, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga Shobha
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Publication number: 20160359013Abstract: A bipolar junction transistor comprises a semiconductor layer disposed on an insulating material, at least a portion of the semiconductor layer forming a base region. The bipolar junction transistor further comprises a transistor emitter laterally disposed on a first side of the base region, where in the transistor emitter is a first doping type and has a first width, and wherein the first width is a lithographic feature size. The bipolar junction transistor further comprises a transistor collector laterally disposed on a second side of the base region, wherein the transistor collector is the first doping type and the first width. The bipolar junction transistor further comprises a central base contact laterally disposed on the base region between the transistor emitter and the transistor collector, wherein the central base contact is a second doping type and has a second width, and wherein the second width is a sub-lithographic feature size.Type: ApplicationFiled: July 18, 2016Publication date: December 8, 2016Inventors: Fabio Carta, Daniel C. Edelstein, Stephen M. Gates, Bahman Hekmatshoartabari, Tak H. Ning
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Patent number: 9508647Abstract: A single damascene interconnect structure which includes a first layer that includes a first dielectric material having a first filled opening that has a barrier layer of a refractory material with Cu filling the first filled opening. Also included is a second layer of a second dielectric material having a second filled opening that has a sidewall layer which includes a compound of a metal, O, and Si such that the metal is Mn, Ti and Al, and with Cu filling the second filled opening. The compound is in direct contact with the second dielectric material. The first layer is adjacent to the second layer and the first filled opening is aligned with the second filled opening so that the first filled opening is a via and the second filled opening is a trench.Type: GrantFiled: October 20, 2015Date of Patent: November 29, 2016Assignee: International Business Machines CorporationInventors: Shyng-Tsong Chen, Daniel C. Edelstein, Takeshi Nogami
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Patent number: 9496239Abstract: A semiconductor structure comprising a first semiconductor structure; a second semiconductor structure; and a silicon-nitride layer configured to bond the first semiconductor structure and second semiconductor structure together. The first semiconductor structure comprises a first wafer; a first dielectric layer; a first interconnect structure; and a first oxide layer. The second semiconductor structure comprises a second wafer; a second dielectric layer; a second interconnect structure; and a second oxide layer. The structure further comprises a first nitride layer residing on a top surface of the first oxide layer formed by a nitridation process of the top surface of the first oxide layer; and a second nitride layer residing on a top surface of the second oxide layer formed by the nitridation process of the top surface of the second oxide layer. Further, the silicon-nitride layer comprises the first nitride layer and the second nitride layer.Type: GrantFiled: December 11, 2015Date of Patent: November 15, 2016Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Chih-Chao Yang
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Publication number: 20160329279Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.Type: ApplicationFiled: July 20, 2016Publication date: November 10, 2016Inventors: Daniel C. EDELSTEIN, Son V. NGUYEN, Takeshi NOGAMI, Deepika PRIYADARSHINI, Hosadurga K. SHOBHA
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Patent number: 9472503Abstract: An electrical device including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure. The liner includes a superlattice structure comprised of a metal oxide layer, a metal layer present on the metal oxide layer, and a metal nitride layer that is present on the metal layer. A first layer of the superlattice structure that is in direct contact with the low-k dielectric material is one of said metal oxide layer and a final layer of the superlattice structure that is in direct contact with the copper including structure is one of the metal nitride layers.Type: GrantFiled: October 15, 2015Date of Patent: October 18, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Donald F. Canaperi, Daniel C. Edelstein, Alfred Grill, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga Shobha
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Patent number: 9455182Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.Type: GrantFiled: August 22, 2014Date of Patent: September 27, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel C. Edelstein, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga K. Shobha
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Patent number: 9425298Abstract: A bipolar junction transistor comprises a semiconductor layer disposed on an insulating material, at least a portion of the semiconductor layer forming a base region. The bipolar junction transistor further comprises a transistor emitter laterally disposed on a first side of the base region, where in the transistor emitter is a first doping type and has a first width, and wherein the first width is a lithographic feature size. The bipolar junction transistor further comprises a transistor collector laterally disposed on a second side of the base region, wherein the transistor collector is the first doping type and the first width. The bipolar junction transistor further comprises a central base contact laterally disposed on the base region between the transistor emitter and the transistor collector, wherein the central base contact is a second doping type and has a second width, and wherein the second width is a sub-lithographic feature size.Type: GrantFiled: January 22, 2015Date of Patent: August 23, 2016Assignee: International Business Machines CorporationInventors: Fabio Carta, Daniel C. Edelstein, Stephen M. Gates, Bahman Hekmatshoartabari, Tak H. Ning
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Patent number: 9406617Abstract: Structures and processes include a single metallization step for forming a metal nitride liner layer suitable for contact formation. The structure and processes generally includes forming a nitrogen-enriched surface in a deposited metal liner layer or forming a nitrogen-enriched surface in the dielectric material prior to deposition of the metal liner layer. In this manner, nitridization of the metal occurs upon deposition of nitrogen ions into the metal liner layer and/or as a function of additional conventional processing in fabricating the integrated circuit such that the deposited nitrogen ions diffuse into at least a portion of the metal liner layer. As a consequence, only a single metal layer deposition step is needed to form the metal liner layer.Type: GrantFiled: November 19, 2015Date of Patent: August 2, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel C. Edelstein, Baozhen Li, Chih-Chao Yang
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Publication number: 20160218200Abstract: A bipolar junction transistor comprises a semiconductor layer disposed on an insulating material, at least a portion of the semiconductor layer forming a base region. The bipolar junction transistor further comprises a transistor emitter laterally disposed on a first side of the base region, where in the transistor emitter is a first doping type and has a first width, and wherein the first width is a lithographic feature size. The bipolar junction transistor further comprises a transistor collector laterally disposed on a second side of the base region, wherein the transistor collector is the first doping type and the first width. The bipolar junction transistor further comprises a central base contact laterally disposed on the base region between the transistor emitter and the transistor collector, wherein the central base contact is a second doping type and has a second width, and wherein the second width is a sub-lithographic feature size.Type: ApplicationFiled: January 22, 2015Publication date: July 28, 2016Inventors: Fabio Carta, Daniel C. Edelstein, Stephen M. Gates, Bahman Hekmatshoartabari, Tak H. Ning
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Publication number: 20160163640Abstract: A structure having fully aligned via connecting metal lines on different Mx levels. The structure may include a first metal line and a second metal line in a first ILD, a cap covering the first ILD, the second metal line and a portion of the first metal line, a second ILD on the cap, and a via that electrically connects the first metal line to a third metal line, wherein the third metal line is above the first metal line and runs perpendicular to the first metal line, the via is fully aligned to the first metal line and the third metal line, and the via electrically connects the first metal line to the third metal line.Type: ApplicationFiled: February 16, 2016Publication date: June 9, 2016Inventors: Daniel C. Edelstein, Nicholas C. Fuller, Elbert E. Huang, Satyanarayana V. Nitta, David L. Rath